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Add dynamic slicing Verilog testcase

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This commit is contained in:
Eddie Hung 2020-03-31 11:51:31 -07:00
parent a0cc795e85
commit 3df66027e0
1 changed files with 12 additions and 0 deletions

12
tests/simple/dynslice.v Normal file
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module dynslice (
input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input [3:0] sel ,
output reg [127:0] dout
);
always @(posedge clk)
begin
dout[ctrl*sel+:16] <= din ;
end
endmodule