yosys/tests/simple/module_scope_case.v at 2e697f5655455fd8ce5fec40b94683a11ade24e8 - mirrors/yosys - Libre-Chip.org

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Zachary Snow 2e697f5655 verilog: check for module scope identifiers during width detection

The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().

2021-06-08 15:03:16 -04:00

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 module top(
 	input wire x,
 	output reg y
 );
 	always @* begin
 		case (top.x)
 : top.y = 0;
 : top.y = 1;
 		endcase
 	end
 endmodule