mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-15 03:35:40 +00:00
4d215665a1
Map $macc_v2 cells (one signed <=27x18 product + one <=48-bit addend)
to MULTALU27X18 with the C addend enabled, so a*b+c maps to a single
DSP block instead of a multiply + fabric adder.
The C addend requires DYN_C_SEL("TRUE") + CSEL=1 (gowin_pack reads the
CSEL port, not the C_SEL parameter).
alumacc + macc techmap run before wreduce for gw5a, so $mul and $add
ports still have matching widths when alumacc tries to merge them.
Running after wreduce breaks the merge: wreduce narrows $mul Y (48->45)
but not $add A (stays 48), and alumacc can't merge mismatched widths.
|
||
|---|---|---|
| .. | ||
| adc.v | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| brams_map_gw5a.v | ||
| cells_latch.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra_gw1n.v | ||
| cells_xtra_gw2a.v | ||
| cells_xtra_gw5a.v | ||
| CMakeLists.txt | ||
| dsp_map.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| macc_map_gw5a.v | ||
| synth_gowin.cc | ||