mirror of
https://github.com/YosysHQ/yosys
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4d215665a1
Map $macc_v2 cells (one signed <=27x18 product + one <=48-bit addend)
to MULTALU27X18 with the C addend enabled, so a*b+c maps to a single
DSP block instead of a multiply + fabric adder.
The C addend requires DYN_C_SEL("TRUE") + CSEL=1 (gowin_pack reads the
CSEL port, not the C_SEL parameter).
alumacc + macc techmap run before wreduce for gw5a, so $mul and $add
ports still have matching widths when alumacc tries to merge them.
Running after wreduce breaks the merge: wreduce narrows $mul Y (48->45)
but not $add A (stays 48), and alumacc can't merge mismatched widths.
56 lines
667 B
CMake
56 lines
667 B
CMake
yosys_pass(synth_gowin
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synth_gowin.cc
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REQUIRES
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abc
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abc9
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alumacc
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autoname
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blackbox
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check
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clean
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deminout
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dfflegalize
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flatten
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fsm
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hierarchy
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hilomap
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iopadmap
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memory
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memory_libmap
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memory_map
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opt
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opt_clean
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opt_expr
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opt_lut_ins
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peepopt
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proc
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read_verilog
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setundef
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share
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simplemap
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sort
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splitnets
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stat
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techmap
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tribuf
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wreduce
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write_json
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write_verilog
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DATA_DIR
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gowin
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DATA_FILES
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cells_map.v
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cells_sim.v
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cells_latch.v
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cells_xtra_gw1n.v
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cells_xtra_gw2a.v
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cells_xtra_gw5a.v
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arith_map.v
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brams_map.v
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brams_map_gw5a.v
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brams.txt
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lutrams_map.v
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lutrams.txt
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dsp_map.v
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macc_map_gw5a.v
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)
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