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4d215665a1
Map $macc_v2 cells (one signed <=27x18 product + one <=48-bit addend)
to MULTALU27X18 with the C addend enabled, so a*b+c maps to a single
DSP block instead of a multiply + fabric adder.
The C addend requires DYN_C_SEL("TRUE") + CSEL=1 (gowin_pack reads the
CSEL port, not the C_SEL parameter).
alumacc + macc techmap run before wreduce for gw5a, so $mul and $add
ports still have matching widths when alumacc tries to merge them.
Running after wreduce breaks the merge: wreduce narrows $mul Y (48->45)
but not $add A (stays 48), and alumacc can't merge mismatched widths.
59 lines
1.2 KiB
Verilog
59 lines
1.2 KiB
Verilog
module \$macc_v2 (A, B, C, Y);
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parameter NPRODUCTS = 0;
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parameter PRODUCT_NEGATED = 1'b0;
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parameter NADDENDS = 0;
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parameter ADDEND_NEGATED = 1'b0;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter C_SIGNED = 0;
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parameter A_WIDTHS = 1;
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parameter B_WIDTHS = 1;
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parameter C_WIDTHS = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTHS-1:0] A;
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input [B_WIDTHS-1:0] B;
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input [C_WIDTHS-1:0] C;
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output [Y_WIDTH-1:0] Y;
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wire _TECHMAP_FAIL_ = !(NPRODUCTS == 1 && NADDENDS == 1 &&
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PRODUCT_NEGATED == 1'b0 && ADDEND_NEGATED == 1'b0 &&
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A_SIGNED && B_SIGNED && C_SIGNED &&
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A_WIDTHS <= 27 && B_WIDTHS <= 18 && C_WIDTHS <= 48);
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wire [47:0] dout_w;
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MULTALU27X18 #(
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.MULT12X12_EN("FALSE"),
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.MULT_RESET_MODE("SYNC"),
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.AREG_CLK("BYPASS"),
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.BREG_CLK("BYPASS"),
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.PREG_CLK("BYPASS"),
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.OREG_CLK("BYPASS"),
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.DYN_C_SEL("TRUE")
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) __TECHMAP_REPLACE__ (
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.DOUT(dout_w),
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.CASO(),
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.SOA(),
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.A(A),
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.SIA(27'd0),
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.B(B),
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.C(C),
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.D(26'd0),
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.CASI(48'd0),
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.ACCSEL(1'b0),
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.PSEL(1'b0),
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.ASEL(1'b0),
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.PADDSUB(1'b0),
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.CSEL(1'b1),
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.CASISEL(1'b0),
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.ADDSUB(2'b00),
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.CLK(2'b00),
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.CE(2'b00),
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.RESET(2'b00)
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);
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assign Y = dout_w;
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endmodule
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