Exact

Exact Union RegExp

Miodrag Milanovic ce280354cf Update CI scripts for CMake ... Co-authored-by: Catherine <whitequark@whitequark.org>		2026-06-03 08:58:11 +00:00
..
dynamic_part_select
.gitignore
abc9.v
abc9.ys	abc9: uniquify blackboxes like whiteboxes (#2695)	2021-03-29 22:02:06 -07:00
abstract_init.ys
abstract_initstates.ys	abstract: Add -initstates option	2025-08-12 15:37:12 +02:00
abstract_state.ys
abstract_value.ys
aiger2.ys
aiger_dff.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v	tests: fix some test warnings	2020-05-25 10:07:58 -07:00
attrib07_func_call.ys	Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.	2019-06-04 10:42:42 +02:00
autoname.ys
blackbox_wb.ys	blackbox: Include whiteboxed modules	2021-03-17 13:58:04 +00:00
box_derive.ys
bufnorm_opt_clean.ys	bufnorm: Refactor and fix incremental bufNormalize	2025-09-29 08:21:28 +02:00
bug1496.ys
bug1531.ys
bug1614.ys
bug1710.ys
bug1745.ys
bug1781.ys
bug1876.ys
bug2014.ys
bug3462.ys
bug3515.v
bug3515.ys
bug3879.ys
bug4082.ys
bug4865.ys
bug4909.ys
cellarray_array_connections.ys
celledges_shift.ys
check.ys
check_2.ys
check_3.ys
check_4.ys
chformal_check.ys	chformal: Add -assert2cover option	2025-06-14 10:54:23 +12:00
chformal_coverenable.ys
chparam.sh
clk2fflogic_effects.sh	Make out of tree build testing possible	2026-05-19 14:26:07 +02:00
clk2fflogic_effects.sv	clk2fflogic: Fix handling of $check cells	2024-02-14 11:42:27 +01:00
const_arg_loop.sv
const_arg_loop.ys
const_func.sv
const_func.ys
const_func_block_var.v
const_func_block_var.ys
const_shift_empty_arg.ys
constant_drive_conflict.ys
constcomment.ys
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
countbits.sv
countbits.ys
cutpoint_blackbox.ys	cutpoint_blackbox.ys: Extra edge case	2025-08-06 18:11:35 +12:00
cutpoint_whole.ys	cutpoint: Re-add whole module optimization	2025-05-06 09:57:34 +12:00
debugon.ys
deminout_unused.ys
design.ys
design1.ys	design: add test	2020-04-16 12:48:40 -07:00
design2.ys
design_equal_fail.ys
design_equal_pass.ys
dynamic_part_select.ys
elab_sys_tasks.sv	Initial implementation of elaboration system tasks	2019-05-03 03:10:43 +03:00
elab_sys_tasks.ys
equiv_assume.ys
equiv_make_make_assert.ys
equiv_opt_multiclock.ys	Add equiv_opt -multiclock	2019-09-11 13:55:59 +01:00
equiv_opt_undef.ys
exec.ys
ezcmdline_dummy_solver
ezcmdline_plugin.cc
ezcmdline_plugin.sh
fib.v
fib.ys
fib_tern.v
fib_tern.ys	verilog: support recursive functions using ternary expressions	2021-02-12 14:43:42 -05:00
formalff_declockgate.ys
fsm-arst.ys
func_port_implied_dir.sv
func_port_implied_dir.ys
gen_if_null.v
gen_if_null.ys	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
generate_mk.py
global_scope.ys
gzip_verilog.v.gz
gzip_verilog.ys
help.ys
hierarchy.sh
hierarchy_defer.ys
hierarchy_generate.ys	add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality)	2024-04-12 13:51:06 +02:00
hierarchy_param.ys
ice40_mince_abc9.ys
integer_range_bad_syntax.ys
integer_real_bad_syntax.ys
json_escape_chars.ys	fix handling of escaped chars in json backend and frontend	2022-02-18 17:13:09 +01:00
json_param_defaults.v
json_param_defaults.ys
json_scopeinfo.ys
keep_hierarchy.ys
lcov.gold
lcov.v	update test to use suggested selection for assertions	2025-07-01 11:46:27 +02:00
lcov.ys	update test to use suggested selection for assertions	2025-07-01 11:46:27 +02:00
logger_cmd_error.sh
logger_error.ys
logger_fail.sh
logger_nowarning.ys	Added back tests for logger	2020-03-13 15:00:18 +01:00
logger_warn.ys
logger_warning.ys
logic_param_simple.ys
mem2reg.ys
memory_word_as_index.data
memory_word_as_index.v
memory_word_as_index.ys
muxcover.ys
muxpack.v
muxpack.ys
muxpack_wide_y.ys
param_struct.ys
peepopt.ys	peepopt: add shiftpow2 pattern	2026-05-31 02:01:32 +02:00
peepopt_formal.ys
plugin.cc
plugin.sh
pmgen_reduce.ys	Add test for pmtest_test "reduce" demo pattern	2019-08-17 14:05:10 +02:00
pmux2shiftx.v
pmux2shiftx.ys
port_sign_extend.v
port_sign_extend.ys
primitives.ys
printattr.ys	printattrs: Add test.	2020-05-27 08:00:00 +00:00
rand_const.sv
rand_const.ys
reg_wire_error.sv
reg_wire_error.ys
rename_scramble_name.ys
rename_unescape.ys
rename_wire_move_to_cell.ys
rtlil_signed_attribute.ys
rtlil_z_bits.ys
scopeinfo.ys
scratchpad.ys
script.ys
setundef.sv
setundef.ys
setundef_selection.ys
setundef_selection_ff.il
setundef_selection_undriven.v
sformatf.ys
shregmap.v
shregmap.ys
signed.ys
signext.ys
sim_const.ys
specify.v
specify.ys
splitnets.ys
src.ys
sta.ys
stat.ys
stat_area_by_width.lib
stat_hierarchy.ys	add Testcases	2025-08-13 14:46:01 +02:00
stat_high_level.ys
stat_high_level2.ys
struct_access.sv
struct_access.ys
sub.v
submod.ys
submod_extract.ys
sv_defines.ys
sv_defines_dup.ys
sv_defines_mismatch.ys
sv_defines_too_few.ys
sv_implicit_ports.sh
svalways.sh	proc: ignore nosync temporaries in always_latch checks	2026-05-26 00:56:07 +08:00
tcl_apis.tcl
tcl_apis.v
tcl_apis.ys
timeest.ys
wrapcell.ys
wreduce.ys
wreduce2.ys
write_gzip.ys
xaiger.ys