3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-18 13:15:46 +00:00
Commit graph

4 commits

Author SHA1 Message Date
Akash Levy
0db45a6796 Reenable VHDL 2026-04-16 04:03:31 -07:00
Akash Levy
3e9a5c68b1 Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
Miodrag Milanovic
7d2857b30f Fix regex checks 2025-10-14 16:04:56 +02:00
N. Engelhardt
4513783a02 add tests 2025-10-14 15:48:16 +02:00