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Author SHA1 Message Date
Eddie Hung
e273ed5275 Wrap SRL{16,32} too 2019-08-20 15:09:38 -07:00
Eddie Hung
808f07630f Wrap LUTRAMs in order to capture comb/seq behaviour 2019-08-20 14:49:11 -07:00
Eddie Hung
c00d72cdb3 Minor refactor 2019-08-20 14:47:58 -07:00
Eddie Hung
0079e9b4a6 Add LUTRAM delays 2019-08-20 13:53:38 -07:00
Eddie Hung
505d062daf Fix use of {CLK,EN}_POLARITY, also add a FIXME 2019-08-20 13:33:31 -07:00
Eddie Hung
8d0cffaf20 Remove mapping rules 2019-08-20 13:11:39 -07:00
Eddie Hung
33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00
Eddie Hung
5eda5fc7eb Remove -icells 2019-08-20 12:41:11 -07:00
Eddie Hung
be9e4f1b67 Use abc_{map,unmap,model}.v 2019-08-20 12:39:11 -07:00
Eddie Hung
c4d4c6db3f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 12:00:12 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 
Refactor abc9 to use port attributes, not module attributes
 2019-08-20 11:59:31 -07:00
Eddie Hung
d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
SergeyDegtyar
71dd412ac5 Fix tests; Remove simulation; 
- Add -map and -assert options for equiv_opt;
	!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
		- dffs;
		- div_mod;
		- latches;
		- mul_pow;
- Add design -load;
- Remove simulations;
 2019-08-20 15:52:25 +03:00
Clifford Wolf
ba71e4f8f2
Merge pull request #1298 from YosysHQ/clifford/pmgen 
Improvements in pmgen
 2019-08-20 11:39:42 +02:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00
Clifford Wolf
6ffb910d12 Add test case for real parameters 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-20 11:38:21 +02:00
Clifford Wolf
c25c1e742b
Merge pull request #1308 from jakobwenzel/real_params 
Handle real values when deriving ast modules
 2019-08-20 11:37:26 +02:00
SergeyDegtyar
153ec0541c Add new tests for ice40 architecture 2019-08-20 07:50:05 +03:00
whitequark
749ff864aa
Merge pull request #1309 from whitequark/proc_clean-fix-1268 
proc_clean: fix order of switch insertion
 2019-08-20 00:45:41 +00:00
Eddie Hung
1f03154a0c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 15:19:32 -07:00
Eddie Hung
526e081342 Add arrival times for SRL outputs 2019-08-19 15:15:43 -07:00
Eddie Hung
45d4b33f0c Output i/o/h extensions even if no boxes or flops 2019-08-19 13:17:31 -07:00
Eddie Hung
b71212ddea Add BRAM arrival times 2019-08-19 12:46:35 -07:00
Eddie Hung
e29df7d5fa Remove debug 2019-08-19 12:44:43 -07:00
Eddie Hung
2f86366087 Add reference to source of Tclktoq timing 2019-08-19 12:39:22 -07:00
Eddie Hung
91687d3fea Add (* abc_arrival *) attribute 2019-08-19 12:33:24 -07:00
Eddie Hung
d02ef8c73f Add 'abc_arrival' attribute for flop outputs 2019-08-19 11:32:18 -07:00
Eddie Hung
f25837f8e8 Update box timings 2019-08-19 11:31:40 -07:00
Eddie Hung
ba2261e21a Move from cell attr to module attr 2019-08-19 11:18:33 -07:00
Eddie Hung
3f4886e7a3 Fix typo 2019-08-19 10:42:00 -07:00
Eddie Hung
7e010834eb Fix typo 2019-08-19 10:41:18 -07:00
Eddie Hung
f42ba811b6 ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc 2019-08-19 10:11:47 -07:00
Eddie Hung
2f4e0a5388 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 10:07:27 -07:00
Eddie Hung
29e4c8bd06 Clarify with 'only' 2019-08-19 10:00:53 -07:00
Eddie Hung
c36fca86f7 Update doc 2019-08-19 09:59:57 -07:00
Eddie Hung
d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung
e301440a0b Use attributes instead of params 2019-08-19 09:51:49 -07:00
whitequark
4a942ba7b9 proc_clean: fix order of switch insertion. 
Fixes #1268.
 2019-08-19 16:44:23 +00:00
Eddie Hung
9bfe924e17 Set abc_flop and use it in toposort 2019-08-19 09:40:01 -07:00
Eddie Hung
10c69f71e9 Use %d 2019-08-19 09:16:20 -07:00
Jakob Wenzel
24971fda87 handle real values when deriving ast modules 2019-08-19 14:17:36 +02:00
Clifford Wolf
4adcbecec5
Merge pull request #1306 from mmicko/gitignore_fix 
Ignore all generated headers for pmgen pass
 2019-08-19 13:09:12 +02:00
Clifford Wolf
21699e5840 Add *.sv to tests/simple_abc9/.gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-19 13:04:57 +02:00
Clifford Wolf
1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00
Clifford Wolf
3edb0abed8
Merge pull request #1305 from YosysHQ/clifford/testfast 
Speed up "make test" and related cleanups
 2019-08-19 12:58:09 +02:00
Eddie Hung
e34f2de55d Merge remote-tracking branch 'origin/master' into clifford/testfast 2019-08-18 21:29:15 -07:00
Eddie Hung
f5170a7eda Removal of more stat calls from tests 2019-08-18 21:28:45 -07:00
Miodrag Milanovic
4a32e29445 Merge remote-tracking branch 'upstream/master' into anlogic_fixes 2019-08-18 11:47:46 +02:00
Miodrag Milanovic
dbe3cb9708 Ignore all generated headers for pmgen pass 2019-08-18 10:49:17 +02:00
whitequark
98a54353b7
Merge pull request #1290 from YosysHQ/eddie/pr1266_again 
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER (retry)
 2019-08-18 08:04:26 +00:00