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Author SHA1 Message Date
Eddie Hung
fcb102d60e Remove .0 from clang-8.0 2019-08-23 12:29:57 -07:00
Eddie Hung
fdc438e551 Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! 2019-08-23 12:29:57 -07:00
Eddie Hung
bf40f2f895 bionic -> xenial as its on whitelist 2019-08-23 12:29:57 -07:00
Eddie Hung
43927e5910 Bump gcc from 4.8 to 4.9 as undefined reference 
... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
 2019-08-23 12:29:50 -07:00
Miodrag Milanovic
55aa444e05 Make macOS depenency clear 2019-08-23 09:15:50 -07:00
Miodrag Milanovic
7fafaa896d do not require boost if pyosys is not used 2019-08-22 11:57:46 -07:00
Chris Shucksmith
68e673d687 require tcl-tk in Brewfile 2019-08-22 11:57:25 -07:00
Clifford Wolf
5e0f6c9ae5 Bump year in copyright notice 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:43:54 +02:00
Miodrag Milanovic
2b4e50ac3d Visual Studio build fix 2019-08-02 17:08:59 +02:00
Miodrag Milanovic
2ec5a3ec92 Fix linking issue for new mxe and pthread 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
ce0de937f4 Fix yosys linking for mxe 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
bf59f31b43 New mxe hacks needed to support 2ca237e 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
e9c5f1b346 Fix formatting for msys2 mingw build using GetSize 2019-08-02 16:55:14 +02:00
David Shah
82a2972068 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 16:45:51 +01:00
Clifford Wolf
1d58bbb79c Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position 
write_verilog: fix placement of case attributes
 2019-07-09 22:19:34 +01:00
David Shah
c8979a3353 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-09 18:51:50 +01:00
Clifford Wolf
8af7ced5cd Merge pull request #1163 from whitequark/more-case-attrs 
More support for case rule attributes
 2019-07-09 18:48:47 +01:00
Clifford Wolf
76f20492a4 Merge pull request #1162 from whitequark/rtlil-case-attrs 
Allow attributes on individual switch cases in RTLIL
 2019-07-09 18:48:38 +01:00
Clifford Wolf
17e0cc010c Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire 
Throw runtime exception when trying to convert inexistend C++ object to Python
 2019-07-09 18:48:23 +01:00
Clifford Wolf
fecd3aa2b1 Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-09 18:47:08 +01:00
Clifford Wolf
d105e2f03f Merge pull request #1154 from whitequark/manual-sync-always 
manual: explain the purpose of `sync always`
 2019-07-09 18:46:58 +01:00
David Shah
4b49c0201e Merge pull request #1153 from YosysHQ/dave/fix_multi_mux 
memory_dff: Fix checking of feedback mux input when more than one mux
 2019-07-09 18:46:39 +01:00
Clifford Wolf
7b298479d4 Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 18:46:28 +01:00
Eddie Hung
fc87c010c5 autotest.sh to define _AUTOTB when test_autotb 2019-07-09 18:46:18 +01:00
Clifford Wolf
ef0823690c Merge pull request #1146 from gsomlo/gls-test-abc-ext 
tests: use optional ABCEXTERNAL when specified
 2019-07-09 18:44:57 +01:00
Eddie Hung
43069e9eb9 Checkout yosys-0.9-rc branch of yosys-tests 2019-07-02 10:06:56 -07:00
Eddie Hung
fdf0e82472 Add missing CHANGELOG entries 2019-06-28 11:16:53 -07:00
Eddie Hung
c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog 
tests: Check that Icarus can parse arch sim models
 2019-06-27 12:31:15 -07:00
Eddie Hung
eab8384ec7 Grr 2019-06-27 11:53:42 -07:00
Eddie Hung
36f3cc9dcc Capitalisation 2019-06-27 11:50:12 -07:00
Eddie Hung
d5cfe341f9 Make CHANGELOG clearer 2019-06-27 11:50:12 -07:00
Eddie Hung
6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135 
Add "pmux2shiftx -norange"
 2019-06-27 11:48:48 -07:00
Eddie Hung
ab7c431905 Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00
Eddie Hung
18acb72c05 Add #1135 testcase 2019-06-27 11:02:52 -07:00
Eddie Hung
760819e10d synth_xilinx -arch -> -family, consistent with older synth_intel 2019-06-27 07:24:47 -07:00
Eddie Hung
ee77ee6973
Merge pull request #1142 from YosysHQ/clifford/fix1132 
Fix handling of partial covers in muxcover
 2019-06-27 07:21:31 -07:00
Eddie Hung
bb4ae8bc66
Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux 
synth_xilinx: Add -nocarry and -nowidelut options
 2019-06-27 06:04:56 -07:00
Eddie Hung
3910bc2ea6 Copy tests from eddie/fix1132 2019-06-27 06:01:50 -07:00
Clifford Wolf
7c14678ec0 Add "pmux2shiftx -norange", fixes #1135 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-27 10:59:12 +02:00
Clifford Wolf
69d810e4a8 Fix handling of partial covers in muxcover, fixes #1132 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-27 09:42:58 +02:00
Eddie Hung
6db181471e Grrr 2019-06-26 10:47:03 -07:00
David Shah
71b046d639 tests: Check that Icarus can parse arch sim models 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 18:46:22 +01:00
Eddie Hung
138989e1a3 Fix spacing 2019-06-26 10:09:18 -07:00
Eddie Hung
cb722e7b58 Oops. Actually use nocarry flag as spotted by @koriakin 2019-06-26 10:06:33 -07:00
Clifford Wolf
0d2b87e3ed
Merge pull request #1137 from mmicko/cell_sim_fix 
Simulation model verilog fix
 2019-06-26 19:06:10 +02:00
Miodrag Milanovic
ea0b6258ab Simulation model verilog fix 2019-06-26 18:34:34 +02:00
Eddie Hung
4ce329aefd synth_ecp5 rename -nomux to -nowidelut, but preserve former 2019-06-26 09:33:48 -07:00
Eddie Hung
7389b043c0 Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux 2019-06-26 09:33:38 -07:00
Clifford Wolf
0b7d648c6a Improve opt_clean handling of unused public wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:54:17 +02:00
Clifford Wolf
1b49380f6b Improve BTOR2 handling of undriven wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:42:00 +02:00