Jannis Harder
fb1c2be76b
verilog: Support void functions
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The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
2023-03-20 12:52:46 +01:00
Miodrag Milanovic
61da330a38
Update tests
2023-03-20 09:58:41 +01:00
Miodrag Milanovic
ff9f1fb86e
Start unification effort for machxo2 and ecp5
2023-03-20 09:58:41 +01:00
Miodrag Milanovic
4d7e9e2e5d
Add additional iopad_external_pin attributes
2023-03-20 09:17:22 +01:00
Miodrag Milanovic
db367bd69e
Add iopad_external_pin to some basic io primitives
2023-03-20 09:17:22 +01:00
Miodrag Milanovic
10589c57bf
insert IO buffers for ECP5, off by default
2023-03-20 09:17:22 +01:00
github-actions[bot]
ceef00c35e
Bump version
2023-03-16 00:17:57 +00:00
Miodrag Milanović
57fb1f51b2
Merge pull request #3704 from jix/enum_values
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verific: Fix enum_values support and signed attribute values
2023-03-15 10:54:19 +01:00
Jannis Harder
390d1c583a
verific: Fix enum_values support and signed attribute values
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This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
2023-03-15 09:51:36 +01:00
github-actions[bot]
101d19bb6a
Bump version
2023-03-11 00:15:30 +00:00
Jannis Harder
c50f641812
Merge pull request #3682 from daglem/struct-member-out-of-bounds
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Out of bounds checking for struct/union members
2023-03-10 16:14:56 +01:00
Stefan Riesenberger
baa3659ea5
ice40: Fix path delay definitions
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Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
2023-03-10 10:48:05 +01:00
Dag Lem
1af7d6121f
Added test for dynamic indexing within struct members
2023-03-08 20:25:39 +01:00
github-actions[bot]
b58664d441
Bump version
2023-03-07 00:18:51 +00:00
N. Engelhardt
7c5ae560a8
Merge pull request #3684 from YosysHQ/fix-GIT_REV
2023-03-06 16:12:36 +01:00
Miodrag Milanovic
368f2984cd
Next dev cycle
2023-03-06 08:50:14 +01:00
Miodrag Milanovic
5f88c218b5
Release version 0.27
2023-03-06 08:47:51 +01:00
Dag Lem
0d3423ddea
Index struct/union members within corresponding wire chunks
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This guards against access to bits outside of struct/union
members via dynamic indexing.
2023-03-05 14:54:17 +01:00
github-actions[bot]
9747e55d95
Bump version
2023-03-02 00:18:47 +00:00
Catherine
3f173c2180
Makefile: fix GIT_REV extraction if Yosys is built as submodule.
2023-03-01 21:17:19 +00:00
N. Engelhardt
981c934b5b
Merge pull request #3690 from whitequark/smtbmc-help-opt
2023-03-01 09:59:01 +01:00
N. Engelhardt
25ebefc2a6
Merge pull request #3692 from nakengelhardt/stat_q_fix
2023-03-01 09:49:36 +01:00
N. Engelhardt
1a3ff0d926
Merge pull request #3688 from pu-cc/gatemate-reginit
2023-03-01 09:49:14 +01:00
N. Engelhardt
57897927ff
stat: pass down quiet arg
2023-02-28 17:12:55 +01:00
Miodrag Milanović
bb28e48136
Merge pull request #3663 from uis246/master
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gowin: Add new types of oscillator
2023-02-28 06:56:01 +01:00
Miodrag Milanović
4ff9063145
Merge pull request #3652 from martell/elvds
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gowin: Add support for emulated differential output
2023-02-28 06:55:25 +01:00
github-actions[bot]
71c59d9fab
Bump version
2023-02-28 00:17:33 +00:00
Catherine
4bb173e256
yosys-smtbmc: support -h/--help (and exit with code 0).
2023-02-27 20:31:00 +00:00
Miodrag Milanović
21e87f7986
Merge pull request #3646 from YosysHQ/lofty/fix-3591
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muxcover: do not add decode muxes with x inputs
2023-02-27 16:26:57 +01:00
N. Engelhardt
842cdad575
Merge pull request #3674 from YosysHQ/fix_wide_case
2023-02-27 16:04:11 +01:00
gatecat
2ab3747cc9
fabulous: Add support for mapping carry chains
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-27 09:50:34 +01:00
Miodrag Milanovic
28c4aac234
run verific tests in test target
2023-02-27 09:27:04 +01:00
Miodrag Milanovic
d8cefec169
Added ranged case check
2023-02-27 09:24:04 +01:00
Miodrag Milanovic
53a4f0fb56
Add test example
2023-02-27 09:24:04 +01:00
Miodrag Milanovic
a30894e5fa
Handle more wide case selector types
2023-02-27 09:24:04 +01:00
github-actions[bot]
8216b23fb7
Bump version
2023-02-24 00:16:59 +00:00
Catherine
ef8ed21a2e
Merge pull request #3685 from YosysHQ/update-abc
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Update abc
2023-02-23 07:57:27 +00:00
Catherine
5d9bd0af92
Update abc.
2023-02-23 01:48:21 +00:00
github-actions[bot]
0f2d226ae9
Bump version
2023-02-21 00:17:40 +00:00
N. Engelhardt
c8966722d2
Merge pull request #3403 from KrystalDelusion/mem-tests
2023-02-20 18:27:24 +01:00
KrystalDelusion
f80920bd9f
Genericising bug1836.ys
2023-02-21 05:23:16 +13:00
KrystalDelusion
445a801a85
bug3205.ys removed
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Made redundant by TDP test(s) in memories.ys
2023-02-21 05:23:16 +13:00
KrystalDelusion
51c2d476c2
Removing extra default_nettype lines
2023-02-21 05:23:16 +13:00
KrystalDelusion
8f6a06951c
Fix for sync_ram_sdp not being final module
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Explicitly declare -top in synth_intel_alm.
2023-02-21 05:23:16 +13:00
KrystalDelusion
7f033d3c1f
More tests in memlib/generate.py
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Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features.
2023-02-21 05:23:15 +13:00
KrystalDelusion
af1b9c9e07
Tests for ram_style = "huge"
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iCE40 SPRAM and Xilinx URAM
2023-02-21 05:23:15 +13:00
KrystalDelusion
de2f140c09
Testing TDP synth mapping
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New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
2023-02-21 05:23:15 +13:00
KrystalDelusion
48f4e09202
Asymmetric port ram tests with Xilinx
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Uses verilog code from User Guide 901 (2021.1)
2023-02-21 05:23:14 +13:00
KrystalDelusion
ac5fa9a838
Addings tests for #1836 and #3205
2023-02-21 05:23:14 +13:00
Dag Lem
79043cb849
Out of bounds checking for struct/union members
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Currently, only constant indices are checked.
2023-02-19 23:25:08 +01:00
