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1005 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Clifford Wolf
a4d72de91d Some fixes in libs/minisat (thanks to Siesh1oo) 2014-03-12 23:28:10 +01:00
Siesh1oo
8127d5e8c3 - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). 
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
 - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
 2014-03-12 23:17:14 +01:00
Clifford Wolf
3152863479 Fixed dependencies of "make test" 2014-03-12 10:46:27 +01:00
Clifford Wolf
94c1307c26 Added libs/minisat (copy of minisat git master) 2014-03-12 10:17:51 +01:00
Clifford Wolf
9087ece97c OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:52:37 +01:00
Clifford Wolf
7aa2d746b7 Merged addition of SED makefile variable from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:42:58 +01:00
Clifford Wolf
91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf
9992026a8d Added support for `line compiler directive 2014-03-11 14:06:57 +01:00
Clifford Wolf
fa75c8286e Fixed memory corruption in passes/abc/blifparse.cc 2014-03-11 13:09:01 +01:00
Clifford Wolf
bada3ee815 Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh 2014-03-11 11:59:58 +01:00
Clifford Wolf
4fd1a4c12b Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog) 2014-03-11 11:39:30 +01:00
Clifford Wolf
78c64a6401 Fixed a typo in RTLIL::Module::addReduce... 2014-03-10 12:07:26 +01:00
Clifford Wolf
5a15539c9b Improved verific command (added support for some operators) 2014-03-10 12:06:57 +01:00
Clifford Wolf
c71791a1ff Improvements in verific command 2014-03-10 03:03:08 +01:00
Clifford Wolf
fdef064b1d Added RTLIL::Module::add... helper methods 2014-03-10 03:02:27 +01:00
Clifford Wolf
8d06f9f2fe Added "verific" command 2014-03-09 20:40:04 +01:00
Clifford Wolf
fcae92868d Fixed dumping of timing() { .. } block in libparse 2014-03-09 15:16:07 +01:00
Clifford Wolf
22aabe05c9 Verbose reading of liberty and constr files in ABC pass 2014-03-09 15:15:38 +01:00
Clifford Wolf
e3b11ea2d6 Fixed bug in freduce command 2014-03-07 18:44:23 +01:00
Clifford Wolf
6f8865d81a Some minor code cleanups in freduce command 2014-03-07 18:29:04 +01:00
Clifford Wolf
620d51d9f7 Bugfix in ilang frontend autoidx recovery 2014-03-07 17:19:14 +01:00
Clifford Wolf
f7bd0a5232 Use log_abort() and log_assert() in BTOR backend 2014-03-07 15:56:10 +01:00
Clifford Wolf
54d74cf616 Added freduce -dump 2014-03-06 22:06:58 +01:00
Clifford Wolf
da5859a674 Added freduce -stop 2014-03-06 18:14:26 +01:00
Clifford Wolf
4d07f88258 Fixed gcc compiler warning 2014-03-06 16:37:19 +01:00
Clifford Wolf
9b9c3327cc Fixed undef handling in opt_reduce 2014-03-06 14:18:34 +01:00
Clifford Wolf
973507d85b Fixes for improved techmap of shifts with large B inputs 2014-03-06 13:33:12 +01:00
Clifford Wolf
97710ffad5 Fixed use of frozen literals in SatGen 2014-03-06 13:08:44 +01:00
Clifford Wolf
8406e7f7b6 Strictly zero-extend unsigned A-inputs of shift operations in techmap 2014-03-06 12:15:44 +01:00
Clifford Wolf
1ecaf1bb76 Added techmap -max_iter option 2014-03-06 12:15:17 +01:00
Clifford Wolf
d7f29bb23f Improved techmap of shift with wide B inputs 2014-03-06 12:14:20 +01:00
Clifford Wolf
a1bfde8c5e Strictly zero-extend unsigned A-inputs of shift operations 2014-03-06 11:53:37 +01:00
Clifford Wolf
b1b8fe3a56 Switched to EZMINISAT_SIMPSOLVER as default SAT solver 2014-03-05 19:57:10 +01:00
Clifford Wolf
09805ee9ec Include id2ast pointers when dumping AST 2014-03-05 19:56:31 +01:00
Clifford Wolf
d6a01fe412 Fixed merging of compatible wire decls in AST frontend 2014-03-05 19:55:58 +01:00
Clifford Wolf
de7bd12004 Bugfix in recursive AST simplification 2014-03-05 19:45:33 +01:00
Clifford Wolf
96e753041d fixed freduce for Minisat::SimpSolver: use frozen_literal() 2014-03-03 02:14:27 +01:00
Clifford Wolf
d5bd93997c ezSAT: Added frozen_literal() API 2014-03-03 02:13:17 +01:00
Clifford Wolf
895e9fc70c ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressions 2014-03-03 02:12:45 +01:00
Clifford Wolf
d500bd749f Added ezSAT::eliminated API to help the SAT solver remember eliminated variables 2014-03-01 21:00:34 +01:00
Clifford Wolf
23f0a12c72 ezSAT bugfix: don't call virtual methods in base class constructor 2014-03-01 20:59:00 +01:00
Clifford Wolf
edc2146056 Removed ezSAT::assumed() API 2014-03-01 20:55:06 +01:00
Clifford Wolf
e3debea4e6 Removed ezSAT built-in brute-froce solver 2014-03-01 20:53:09 +01:00
Clifford Wolf
ef90236a5d Fixed vhdl2verilog temp dir name 2014-03-01 17:48:15 +01:00
Clifford Wolf
04999f4af0 Fixed vhdl2verilog help message 2014-03-01 17:47:19 +01:00
Clifford Wolf
9e99984336 Fixed const folding of $bu0 cells 2014-02-27 04:09:32 +01:00
Clifford Wolf
ae5032af84 Fixed bit-extending in $mux argument (use $bu0 instead of $pos) 2014-02-26 21:32:19 +01:00
Clifford Wolf
aaaa604853 Added support for $bu0 to SatGen 2014-02-26 21:31:34 +01:00
Clifford Wolf
6bc94b7eb2 Don't blow up constants unneccessarily in Verilog frontend 2014-02-24 12:41:25 +01:00