2420 commits

Author	SHA1	Message	Date
Emil J	d901b28d2c	Merge pull request #4546 from NachtSpyder04/main ... [Docs]:Add new cell type help messages	2024-08-19 15:50:41 +02:00
David Lanzendörfer	d1b767ea8b	Adding missing to Gowin tech files ... Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip design for my Sipeed Tang FPGA fails.	2024-08-18 19:38:31 +01:00
NachtSpyder04	aa60255e0e	update help messages that went beyond line length limit	2024-08-18 20:27:35 +05:30
Saish Karole	34aabd56cc	Apply suggestions from code review ... Co-authored-by: Martin Povišer <povik@cutebit.org>	2024-08-18 20:12:53 +05:30
Saish Karole	d80d4dc51c	[Docs]:Add new cell type help messages (#1) ... * add shift operators description * update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators	2024-08-17 15:47:00 +05:30
Miodrag Milanovic	54d237ff82	add min_ce_use and min_srst_use parameters	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	14e43139cb	Run opt_merge, helps with inverted reset/load signals	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	220ddeac4d	Set -mince and -minsrst	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	dbf1d037e8	Cleanup	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	7bf623a0c7	Fix simulation model warnings	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	262ad03cd3	Add iopads by default add option to disable and keep old one for compatibility	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	8f806c0d12	Added DDFR support	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	1a6e5c671f	Add meminit handling for NX_RFB_U	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	6876a27547	Add NX_DFR simulation model	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	eb30be6189	Impulse does not support these types but NG-ULTRA architecture does	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	7601dc740b	Some memory types are only supported on NG-LARGE	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	4372487a6f	raw must be 16 bits for nx tools to work	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	f8ae93c0ea	run setundef for all x inputs	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	40f05009e3	Fix CY chaining and CI injection	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	596506b88b	Add NX_XCDC_U to wrappers	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	8909a42796	Better wire check	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	5766555642	Support brams with initialization	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	4aaab8f395	start adding wfg model	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	41a86fdb2c	fix	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	f4d8ea4c40	Start adding RFB simulation models	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	8eb099c1f4	remove debug attribute	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	829dd62054	block ram mapping for standard modes	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	9d6b47466f	Add RF initialization	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	7e4aef06e4	Add register file mapping	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	11449ec493	Cleanup not connected ports	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	f9f68c3cd1	Split sim models into multiple files and implement few	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	04d3672121	No need for LOC	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	41ae513d60	support other I/O configurations	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	645888cff5	cleanup	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	9a9190b67d	enable dff context initialization	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	dc16bdd85b	DFF reset and context must be in sync	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	cb45f8b69d	Fixed of mapping and initialization	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	198fc963ca	Add new DFF types, and added "-nodffe" option	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	0c4bbf7e4b	Fix existing DFF mapping and add new types	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	94675a5e0b	Fix dff simulation model	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	606439b44c	do not leave NX_RAM empty to prevent removing it	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	4cb8e62626	Properly map ff ram	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	1591d258a9	Made NX_CY model more robust	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	dac4f04460	add latch mapping, and remove aldff for now	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	cf21b48bfd	fix co on nx_cy	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	31f943513b	set add_carry property and all inputs to 0	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	b6f7383736	break long chains	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	ab32dde81b	optimized	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	da6a62f3a0	Initial carry chain handling pass	2024-08-15 17:50:36 +02:00
Miodrag Milanovic	474ed28aee	added no-rw-check, and new rfb models	2024-08-15 17:50:36 +02:00