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12783 commits 97 branches 53 tags 41 MiB
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8 commits

Author SHA1 Message Date
N. Engelhardt f9c8978128 add example memory test 2023-12-04 15:52:03 +01:00
N. Engelhardt b80b1ab8b6 merge brams_final_map.v into brams_map.v 2023-12-04 15:52:02 +01:00
N. Engelhardt 20d864bbde add dsp inference 2023-12-04 15:52:02 +01:00
N. Engelhardt 6682693888 change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-12-04 15:52:02 +01:00
N. Engelhardt 48c1fdc33d add qlf_k6n10f architecture + bram inference 
(Copied from QuickLogic Yosys plugin repo)
 2023-12-04 15:52:02 +01:00
N. Engelhardt 98769010af synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
Lofty dce037a62c quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
Lofty f4298b057a quicklogic: PolarPro 3 support 
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
 2021-03-18 13:28:16 +01:00