mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 09:34:09 +00:00
f4298b057a
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
10 lines
624 B
Makefile
10 lines
624 B
Makefile
OBJS += techlibs/quicklogic/synth_quicklogic.o
|
|
|
|
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v))
|
|
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v))
|
|
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v))
|
|
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v))
|
|
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v))
|
|
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v))
|
|
$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v))
|