220 commits

Author	SHA1	Message	Date
Clifford Wolf	f6629b9c29	Optimize memory address port width in wreduce and memory_collect, not verilog front-end	2016-08-19 18:38:25 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Clifford Wolf	11f7b8a2a1	Added opt_expr support for div/mod by power-of-two	2016-05-29 12:17:36 +02:00
Clifford Wolf	0d2923cccd	Connections between inputs and inouts are driven by the input	2016-04-26 19:49:05 +02:00
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Clifford Wolf	1565d1af69	Fixed performance bug in "share" pass	2016-04-21 19:47:25 +02:00
Clifford Wolf	f38ca3e18f	Improvements in opt_expr	2016-04-21 14:23:04 +02:00
Clifford Wolf	6cafd08ac1	Improved opt_merge support for $pmux cells	2016-03-31 09:58:55 +02:00
Clifford Wolf	e2f6d61c00	Typo fixes in opt_expr and opt_merge	2016-03-31 09:56:56 +02:00
Clifford Wolf	ec93680bd5	Renamed opt_share to opt_merge	2016-03-31 08:52:49 +02:00
Clifford Wolf	1d0f0d668a	Renamed opt_const to opt_expr	2016-03-31 08:46:56 +02:00
Andrew Zonenberg	dd7204c0bd	Fixed typo in log message	2016-03-30 20:30:03 -07:00
Clifford Wolf	d6592d5b99	Use alphanumerical order instead of idstring idx in opt_clean compare_signals()	2016-02-02 09:16:18 +01:00
Clifford Wolf	ccdbf41be6	Improvements in wreduce	2015-10-31 13:39:30 +01:00
Clifford Wolf	207736b4ee	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
Clifford Wolf	2a0f577f83	Fixed handling of driver-driver conflicts in wreduce	2015-10-24 13:44:35 +02:00
Clifford Wolf	1d83854d84	Bugfixes in handling of "keep" attribute on wires	2015-10-15 14:57:28 +02:00
Clifford Wolf	82028c42e0	Added wreduce $mul support and fixed signed $mul opt_const bug	2015-09-25 17:27:06 +02:00
Clifford Wolf	51e1295d79	Added detection of "mux inverter" chains in opt_const	2015-09-18 11:55:31 +02:00
Clifford Wolf	e7c018e5d1	Fixed sharing of $memrd cells	2015-09-12 16:01:20 +02:00
Clifford Wolf	b10ea0550d	gcc-4.6 build fixes	2015-09-01 12:51:23 +02:00
Clifford Wolf	f43815054e	Properly clean up unused "init" attributes	2015-08-18 13:50:15 +02:00
Clifford Wolf	ae09c89f62	Fixed opt_clean handling of inout ports	2015-08-16 09:50:17 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	c43f38c81b	Improved handling of "keep" attributes in hierarchical designs in opt_clean	2015-08-12 14:10:14 +02:00
Clifford Wolf	667b015018	Merge pull request #70 from gaomy3832/bugfix ... Remove unused blackbox modules in opt_clean.	2015-08-12 08:45:04 +02:00
Mingyu Gao	cbda56d178	Remove unused blackbox modules in opt_clean.	2015-08-11 09:51:08 -07:00
Mingyu Gao	8c4c62f3e1	Bugfix for cell hash cache option in opt_share.	2015-08-11 11:40:23 +02:00
Clifford Wolf	2185125760	Added missing ct_all setup to opt_clean	2015-08-11 07:54:32 +02:00
Mingyu Gao	021b4a2436	Bugfix for cell hash cache option in opt_share.	2015-08-10 13:01:44 -07:00
Clifford Wolf	2a613b1b66	Some cleanups in opt_rmdff	2015-07-25 12:09:57 +02:00
Clifford Wolf	914ae3401e	Improved $adff simplification	2015-07-24 14:12:50 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	053058d781	Added opt_const -clkinv	2015-07-01 10:49:21 +02:00
Clifford Wolf	08f9b38a9c	Added opt_share -share_all	2015-05-31 14:24:34 +02:00
Clifford Wolf	4b6221478e	Added simple $dlatch support to opt_rmdff	2015-05-23 09:45:48 +02:00
Clifford Wolf	e122c2644e	preserve used $-wires with init attribute in opt_clean	2015-05-22 08:20:29 +02:00
Clifford Wolf	f483dce7c2	Added $eq/$neq -> $logic_not/$reduce_bool optimization	2015-04-29 07:28:15 +02:00
Clifford Wolf	9041f34233	Improved handling of init values in opt_rmdff ... based on a patch by Mingyu Gao, user gaomy3832 on github	2015-04-18 08:04:31 +02:00
Clifford Wolf	e305d85807	Added handling of bool-output cells to "wreduce"	2015-04-13 19:27:49 +02:00
Clifford Wolf	1f1deda888	Added non-std verilog assume() statement	2015-02-26 18:47:39 +01:00
Clifford Wolf	9ae21263f0	Some cleanups in "clean"	2015-02-24 22:31:30 +01:00
Clifford Wolf	4e6ca7760f	Replaced ezDefaultSAT with ezSatPtr	2015-02-21 12:15:41 +01:00
Clifford Wolf	024aa559e2	wreduce help typo fix	2015-02-17 13:02:16 +01:00
Clifford Wolf	0748ef638d	Bugfix in wreduce	2015-02-16 09:08:00 +01:00
Clifford Wolf	910556560f	Added $meminit cell type	2015-02-14 10:23:03 +01:00
Clifford Wolf	87819c62fa	Less aggressive "share" defaults	2015-02-10 20:51:37 +01:00
Clifford Wolf	8805c24640	Fixed opt_clean performance bug	2015-02-04 16:34:06 +01:00
Clifford Wolf	a8f4a099b5	Using design->selected_modules() in opt_*	2015-02-03 23:45:01 +01:00