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Code Activity
yosys/passes/opt
History
Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
..
Makefile.inc Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
opt.cc Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
opt_clean.cc After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
opt_expr.cc Added opt_expr support for div/mod by power-of-two 2016-05-29 12:17:36 +02:00
opt_merge.cc Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
opt_muxtree.cc Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
opt_reduce.cc Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
opt_rmdff.cc Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
share.cc Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
wreduce.cc Optimize memory address port width in wreduce and memory_collect, not verilog front-end 2016-08-19 18:38:25 +02:00