420 commits

Author	SHA1	Message	Date
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	4755e14e7b	Added copy-constructor-like module->addCell(name, other) method	2014-07-26 00:38:44 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	c762050e7f	Added RTLIL::SigSpec is_chunk()/as_chunk() API	2014-07-25 14:23:10 +02:00
Clifford Wolf	6aa792c864	Replaced more old SigChunk programming patterns	2014-07-24 23:10:58 +02:00
Clifford Wolf	22ede43b3f	Small changes regarding cover() and check() in SigSpec	2014-07-24 04:46:36 +02:00
Clifford Wolf	82fa356037	Added hashing to RTLIL::SigSpec relational and equal operators	2014-07-23 23:58:03 +02:00
Clifford Wolf	2a41afb7b2	Added RTLIL::SigSpec::repeat()	2014-07-23 21:34:14 +02:00
Clifford Wolf	c094c53de8	Removed RTLIL::SigSpec::optimize()	2014-07-23 20:32:28 +02:00
Clifford Wolf	a62c21c9c6	Removed RTLIL::SigSpec::expand() method	2014-07-23 19:34:51 +02:00
Clifford Wolf	4e802eb7f6	Fixed all users of SigSpec::chunks_rw() and removed it	2014-07-23 15:36:09 +02:00
Clifford Wolf	85db102e13	Replaced RTLIL::SigSpec::operator!=() with inline version	2014-07-23 15:35:09 +02:00
Clifford Wolf	ec923652e2	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	2014-07-23 09:52:55 +02:00
Clifford Wolf	260c19ec5a	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	2014-07-23 09:34:47 +02:00
Clifford Wolf	c61467a32c	Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)	2014-07-23 08:59:54 +02:00
Clifford Wolf	9e94f41b89	SigSpec refactoring: Added RTLIL::SigSpecIterator	2014-07-22 23:49:26 +02:00
Clifford Wolf	f80da7b41d	SigSpec refactoring: added RTLIL::SigSpec::operator[]	2014-07-22 22:54:03 +02:00
Clifford Wolf	a97be0828a	Removed RTLIL::SigChunk::compare()	2014-07-22 21:40:52 +02:00
Clifford Wolf	08e1e25169	SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api	2014-07-22 21:33:52 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	7bffde6abd	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	2014-07-22 20:39:38 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	16e5ae0b92	SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	361e0d62ff	Replaced depricated NEW_WIRE macro with module->addWire() calls	2014-07-21 12:42:02 +02:00
Clifford Wolf	1d88f1cf9f	Removed deprecated module->new_wire()	2014-07-21 12:35:06 +02:00
Clifford Wolf	54b0f2e659	Added module->remove(), module->addWire(), module->addCell(), cell->check()	2014-07-21 12:02:55 +02:00
Clifford Wolf	e57db5e9b2	Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion	2014-07-20 11:01:04 +02:00
Clifford Wolf	efa7884026	Added SIZE() macro	2014-07-20 10:36:14 +02:00
Clifford Wolf	a721f7d768	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	2014-07-18 11:36:34 +02:00
Clifford Wolf	2d69c309f9	Added function-like cell creation helpers	2014-07-18 10:27:06 +02:00
Clifford Wolf	d4a1b0af5b	Added support for dlatchsr cells	2014-03-31 14:14:40 +02:00
Clifford Wolf	b7c71d92f6	Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API	2014-03-15 14:35:29 +01:00
Clifford Wolf	77e5968323	Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API	2014-03-14 11:45:44 +01:00
Clifford Wolf	fdef064b1d	Added RTLIL::Module::add... helper methods	2014-03-10 03:02:27 +01:00
Clifford Wolf	fa295a4528	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	2014-02-06 19:22:46 +01:00
Clifford Wolf	f9c4d33909	Added RTLIL::SigSpec::to_single_sigbit()	2014-02-02 21:35:26 +01:00
Clifford Wolf	651ce67d97	Added select -assert-none and -assert-any	2014-01-17 16:34:50 +01:00
Clifford Wolf	eec2cd1e78	Added RTLIL::SigSpec::optimized() API	2014-01-03 02:43:31 +01:00
Clifford Wolf	c69c416d28	Added $bu0 cell (for easy correct $eq/$ne mapping)	2013-12-28 12:02:14 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	ccf083e5b0	Fixed uninitialized const flags bug	2013-12-07 16:56:34 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	532091afcb	Added more generic _TECHMAP_ wire mechanism to techmap pass	2013-11-23 15:58:06 +01:00
Clifford Wolf	8e58bb330d	Added SigBit struct and refactored RTLIL::SigSpec::extract	2013-11-22 04:07:13 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00