420 commits

Author	SHA1	Message	Date
Clifford Wolf	ca87116449	More idstring sort_by_* helpers and fixed tpl ordering in techmap	2014-08-15 02:40:46 +02:00
Clifford Wolf	978a933b6a	Added RTLIL::SigSpec::to_sigbit_map()	2014-08-14 23:14:47 +02:00
Clifford Wolf	2f44d8ccf8	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	2014-08-14 22:32:18 +02:00
Clifford Wolf	1bf7a18fec	Added module->ports	2014-08-14 16:22:52 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	e5ac8fdf2b	Fixed SigBit(RTLIL::Wire *wire) constructor	2014-08-12 15:39:48 +02:00
Clifford Wolf	523df73145	Added support for truncating of wires to wreduce pass	2014-08-05 14:47:03 +02:00
Clifford Wolf	ebbbe7fc83	Added RTLIL::IdString::in(...)	2014-08-04 15:40:07 +02:00
Clifford Wolf	8e7361f128	Removed at() method from RTLIL::IdString	2014-08-02 19:08:02 +02:00
Clifford Wolf	04727c7e0f	No implicit conversion from IdString to anything else	2014-08-02 18:58:40 +02:00
Clifford Wolf	768eb846c4	More bugfixes related to new RTLIL::IdString	2014-08-02 18:14:21 +02:00
Clifford Wolf	08392aad8f	Limit size of log_signal buffer to 100 elements	2014-08-02 15:52:21 +02:00
Clifford Wolf	e590ffc84d	Improvements in new RTLIL::IdString implementation	2014-08-02 15:44:10 +02:00
Clifford Wolf	60f3dc9923	Implemented new reference counting RTLIL::IdString	2014-08-02 15:11:35 +02:00
Clifford Wolf	97ad0623df	Fixed memory corruption related to id2cstr()	2014-08-02 13:34:07 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	14412e6c95	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
Clifford Wolf	d13eb7e099	Added ModIndex helper class, some changes to RTLIL::Monitor	2014-08-01 17:14:32 +02:00
Clifford Wolf	97a17d39e2	Packed SigBit::data and SigBit::offset in a union	2014-08-01 15:25:42 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	cd9407404a	Added RTLIL::Monitor	2014-07-31 14:45:14 +02:00
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	2541489105	Added techmap CONSTMAP feature	2014-07-30 22:04:30 +02:00
Clifford Wolf	a7c6b37abf	Added "kernel/yosys.h" and "kernel/yosys.cc"	2014-07-30 14:10:15 +02:00
Clifford Wolf	03c96f9ce7	Added "techmap -map %{design-name}"	2014-07-29 16:35:13 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	3c45277ee0	Added wire->upto flag for signals such as "wire [0:7] x;"	2014-07-28 12:12:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	d86a25f145	Added std::initializer_list<> constructor to SigSpec	2014-07-28 10:52:58 +02:00
Clifford Wolf	c4bdba78cb	Added proper Design->addModule interface	2014-07-27 21:12:09 +02:00
Clifford Wolf	cbc3a46a97	Added RTLIL::SigSpecConstIterator	2014-07-27 14:47:23 +02:00
Clifford Wolf	675cb93da9	Added RTLIL::Module::wire(id) and cell(id) lookup functions	2014-07-27 11:18:31 +02:00
Clifford Wolf	0bd8fafbd2	Added RTLIL::Design::modules()	2014-07-27 11:18:30 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	d088854b47	Added conversion from ObjRange to std::vector and std::set	2014-07-27 11:18:30 +02:00
Clifford Wolf	1c8fdaeef8	Added RTLIL::ObjIterator and RTLIL::ObjRange	2014-07-27 11:18:30 +02:00
Clifford Wolf	ddc5b41848	Using std::move() in SigSpec move constructor	2014-07-27 09:20:59 +02:00
Clifford Wolf	7f3dc86ecd	Added RTLIL::SigSpec move constructor and move assignment operator	2014-07-27 02:11:57 +02:00
Clifford Wolf	c91570bde3	Mostly cosmetic changes to rtlil.h	2014-07-27 02:00:04 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	d68c993ed2	Changed more code to the new RTLIL::Wire constructors	2014-07-26 21:30:38 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	cd6574ecf6	Added some missing "const" in rtlil.h	2014-07-26 15:58:22 +02:00
Clifford Wolf	7ac9dc7f6e	Added RTLIL::Module::connections()	2014-07-26 15:58:21 +02:00
Clifford Wolf	b03aec6e32	Added RTLIL::Module::connect(const RTLIL::SigSig&)	2014-07-26 14:31:47 +02:00
Clifford Wolf	3719281ed4	Automatically pack SigSpec on copy/assign	2014-07-26 13:59:30 +02:00
Clifford Wolf	e75e495c2b	Added new RTLIL::Cell port access methods	2014-07-26 12:22:58 +02:00