11 commits

Author	SHA1	Message	Date
Eddie Hung	991c2ca95b	Add comment on why we have to match for clock-enable/reset muxes	2019-10-05 08:56:37 -07:00
Eddie Hung	792cd31052	Add comments for xilinx_dsp_cascade	2019-10-04 22:31:04 -07:00
Eddie Hung	aebbfffd71	Ooops AREG and BREG to default to -1	2019-09-27 11:57:53 -07:00
Eddie Hung	5b9deef10d	Do not always zero out C (e.g. during cascade breaks)	2019-09-26 13:59:05 -07:00
Eddie Hung	58f31096ab	Zero out ports	2019-09-26 13:40:38 -07:00
Eddie Hung	af59856ba1	xilinx_dsp_cascade to also cascade AREG and BREG	2019-09-26 13:29:18 -07:00
Eddie Hung	832216dab0	Try recursive pmgen for P cascade	2019-09-26 12:09:57 -07:00
Eddie Hung	d0dbbc2605	Move unextend initialisation later	2019-09-23 13:26:34 -07:00
Eddie Hung	95644b00cb	OPMODE is port not param	2019-09-20 12:37:29 -07:00
Eddie Hung	0bca366bcd	WIP for xiinx_dsp_cascadeAB	2019-09-20 12:07:14 -07:00
Eddie Hung	ed187ef1cf	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	2019-09-20 10:00:09 -07:00