2 commits

Author	SHA1	Message	Date
Zachary Snow	f55fbb5803	verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections ... - AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate RTLIL that exclusively reference a signed wire. - AST_CONCAT may also contain a memory write.	2025-09-23 15:04:09 +02:00
Zachary Snow	e833c6a418	verilog: use derived module info to elaborate cell connections ... - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change	2021-10-25 18:25:50 -07:00