yosys/tests/simple/memwr_port_connection.sv at f55fbb5803deca7b19e19162c4e83cb31cb977a6 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-10-10 01:41:59 +00:00

Zachary Snow f55fbb5803 verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.

2025-09-23 15:04:09 +02:00

15 lines

260 B

Systemverilog

Raw Blame History

 module producer(
     output logic [3:0] out
 );
     assign out = 4'hA;
 endmodule
 module top(
     output logic [3:0] out0, out1
 );
     logic [3:0] v[1:0];
     producer p0(v[0]);
     producer p1({v[1]});
     assign out0 = v[0];
     assign out1 = v[1];
 endmodule