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Author SHA1 Message Date
Marcelina Kościelnicka
a786091b46 achronix: Use dfflegalize. 2020-07-14 23:12:16 +02:00
whitequark
a5cf000377 cxxrtl: fix typo. NFC. 2020-07-14 16:10:30 +00:00
Marcelina Kościelnicka
3050454d6e anlogic: Use dfflegalize. 2020-07-14 05:02:50 +02:00
Marcelina Kościelnicka
3209c0762a intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
Lofty
a3a90f6377 Revert "intel_alm: direct M10K instantiation" 
This reverts commit 09ecb9b2cf.
 2020-07-13 18:05:38 +02:00
whitequark
38b814b525
Merge pull request #2263 from whitequark/cxxrtl-capi-eval-commit 
cxxrtl: expose eval() and commit() via the C API
 2020-07-13 02:44:36 +00:00
whitequark
5349a922e4 cxxrtl: expose eval() and commit() via the C API. 2020-07-12 23:34:18 +00:00
Marcelina Kościelnicka
347dd01c2f xilinx: Fix srl regression. 
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9.  Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
 2020-07-12 23:41:27 +02:00
Marcelina Kościelnicka
b33744b03a proc_dlatch: Remove init values for combinatorial processes. 
Fixes #2258.
 2020-07-12 18:50:30 +02:00
Marcelina Kościelnicka
240351c44e dfflegalize: Gather init values from all wires. 
Skipping non-selected wires is unsound in an obvious way.
 2020-07-12 17:39:13 +02:00
clairexen
eef0ec6aed
Merge pull request #2256 from YosysHQ/claire/fix2241 
Add AST_EDGE support to AstNode::detect_latch()
 2020-07-10 19:07:50 +02:00
Claire Wolf
f9ed09423e Add AST_EDGE support to AstNode::detect_latch(), fixes #2241 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-07-10 18:41:13 +02:00
Kamil Rakoczy
d77b3305d8 Fix S/R conflicts 
This commit fixes S/R conflicts introduced by commit 6f9be93.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-10 15:03:53 +02:00
Kamil Rakoczy
0ffaddee5e Fix R/R conflicts 
This commit fixes R/R conflicts introduced by commit 7e83a51.
Parameter logic is already defined as part of `param_range_type` rule.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-10 15:03:01 +02:00
Kamil Rakoczy
de649b9194 Revert "Revert PRs #2203 and #2244." 
This reverts commit 9c120b89ac.
 2020-07-10 09:59:48 +02:00
Dan Ravensloft
7dc0439de4 sf2: replace sf2_iobs with {clkbuf,iopad}map 2020-07-09 21:28:52 +01:00
whitequark
c0bcbe1f62
Merge pull request #2255 from whitequark/bison-Werror-conflicts 
verilog_parser: turn S/R and R/R conflicts into hard errors
 2020-07-09 20:17:19 +00:00
whitequark
0e9b889b77
Merge pull request #2254 from whitequark/cxxrtl-extern-c 
cxxrtl: add missing extern "C"
 2020-07-09 20:17:12 +00:00
Marcelina Kościelnicka
edbaf2fdf6 sf2: Use dfflegalize. 2020-07-09 21:56:14 +02:00
whitequark
dc35ef05f9 verilog_parser: turn S/R and R/R conflicts into hard errors. 
Fixes #2253.
 2020-07-09 19:36:59 +00:00
whitequark
9c120b89ac Revert PRs #2203 and #2244. 
This reverts commit 7e83a51fc9.
This reverts commit b422f2e4d0.
This reverts commit 7cb56f34b0.
This reverts commit 6f9be939bd.
This reverts commit 76a34dc5f3.
 2020-07-09 19:36:32 +00:00
whitequark
ab59e33b2b cxxrtl: add missing extern "C". 
This bug was hidden if a header was generated.
 2020-07-09 17:52:52 +00:00
Marcelina Kościelnicka
f313211c32 xilinx: Use dfflegalize. 2020-07-09 18:54:23 +02:00
Marcelina Kościelnicka
7ed9d18907 dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
Lucas Castro
68babb2ae4
Fix issue #2251 (#2252) 
* Fix #2251 - YosysJS ReferenceError: _memset is not defined.
Add '_memset' in emcc EXPORTED_FUNCTIONS in Makefile.
 2020-07-09 18:50:26 +02:00
Marcelina Kościelnicka
32d2cc8c28 clkbufmap: improve input pad handling. 
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
  buffer
 2020-07-09 18:48:01 +02:00
clairexen
802671b22e
Merge pull request #2244 from antmicro/logic 
Add logic type support to parameters
 2020-07-09 18:39:30 +02:00
Marcelina Kościelnicka
03e28f7ab4 clk2fflogic: Consistently treat async control signals as negative hold. 
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
 2020-07-09 18:12:47 +02:00
Marcelina Kościelnicka
e9c2c1b717 dfflegalize: Add special support for const-D latches. 
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q.  Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
 2020-07-09 18:11:32 +02:00
whitequark
000fd08198
Merge pull request #2246 from YosysHQ/mwk/dfflegalize-typo 
dfflegalize: typo fix
 2020-07-07 22:46:37 +00:00
Marcelina Kościelnicka
943147b768 dfflegalize: typo fix 2020-07-07 15:00:52 +02:00
Marcelina Kościelnicka
d5e5d96527 efinix: Use dfflegalize. 2020-07-06 12:28:17 +02:00
Marcelina Kościelnicka
c73ebeb90e gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
Kamil Rakoczy
b422f2e4d0 Add logic param and integer bad syntax tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-06 09:18:48 +02:00
Lukasz Dalek
7e83a51fc9 Support logic typed parameters 
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
 2020-07-06 09:18:48 +02:00
Dan Ravensloft
09ecb9b2cf intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
Marcelina Kościelnicka
af54b8bc61 Naming fixes. 2020-07-05 22:21:59 +02:00
Dan Ravensloft
7f45cab27a synth_gowin: ABC9 support 
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
 2020-07-05 22:07:17 +02:00
Dan Ravensloft
0d4c2f0a65 intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
Marcelina Kościelnicka
b5f3b70cfe
Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40 
ice40: Use dfflegalize.
 2020-07-05 18:50:25 +02:00
Marcelina Kościelnicka
372521ca56 ecp5: Use dfflegalize. 2020-07-05 18:49:41 +02:00
whitequark
0cb6725b6e
Merge pull request #2227 from Ravenslofty/ccache 
Add option to use ccache when building
 2020-07-05 15:53:41 +00:00
Marcelina Kościelnicka
90b89e5ebc
Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init 
gowin: Fix INIT values in sim library.
 2020-07-05 12:02:31 +02:00
Marcelina Kościelnicka
f3f55ae7c2 dfflegalize: Prefer mapping dff to sdff before adff 
This ensures that, when both sync and async FFs are available and abc9
is involved, the sync FFs will be used, and will thus remain available
for sequential synthesis.
 2020-07-05 12:01:43 +02:00
Marcelina Kościelnicka
7afcb72c98 opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. 
Fixes #2221.
 2020-07-05 06:31:58 +02:00
Dan Ravensloft
b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
1fc8c3a0d1 ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
Marcelina Kościelnicka
9beed4d771 gowin: Fix INIT values in sim library. 2020-07-05 03:03:48 +02:00
Dan Ravensloft
01772dec8c gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00
Marcelina Kościelnicka
3ca2de0f77 synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00