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15692 commits 121 branches 59 tags 69 MiB
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Author SHA1 Message Date
Clifford Wolf
db6d78a186 Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr 2017-08-25 16:02:15 +02:00
Clifford Wolf
86df0fb381 Merge branch 'extract_fa' 2017-08-25 13:42:13 +02:00
Clifford Wolf
382cc90c65 Further improve extract_fa (seems to be fully functional now) 2017-08-25 13:41:54 +02:00
Clifford Wolf
0bf612506c Rename "adders" to "extract_fa" 2017-08-25 12:04:40 +02:00
Clifford Wolf
c2d737457a Fix bug in write_smt2 (export logic driving hierarchical cells before exporting regs) 2017-08-25 11:44:48 +02:00
Clifford Wolf
15cdda7c4b Towards more generic "adder" function extractor 2017-08-23 14:20:10 +02:00
Clifford Wolf
51cbec7f75 Add experimental adders pass 2017-08-22 13:52:13 +02:00
Clifford Wolf
d3b3dd8e88 Add hashlib support for hashing of pools 2017-08-22 13:04:33 +02:00
Clifford Wolf
bce0bb6e43 Add consteval support for $_ANDNOT_ and $_ORNOT_ 2017-08-22 13:04:05 +02:00
Clifford Wolf
df3e6e1ec9 Remove some dead code from fsm_map 2017-08-21 15:02:16 +02:00
Clifford Wolf
ca53fba44a Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
Clifford Wolf
d38a64b1cf More intuitive handling of "cd .." for singleton modules 2017-08-19 00:15:12 +02:00
Clifford Wolf
bbdf7d9c66 Add "sim -zinit -rstlen" 2017-08-18 12:54:17 +02:00
Clifford Wolf
35760dd784 Merge branch 'sim' 2017-08-18 11:45:15 +02:00
Clifford Wolf
d30cc60ba9 Add "sim" support for memories 2017-08-18 11:44:50 +02:00
Clifford Wolf
4ba5bd12c6 Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() 2017-08-18 11:40:08 +02:00
Clifford Wolf
0be738eaac Add support for assert/assume/cover to "sim" command 2017-08-18 10:24:14 +02:00
Clifford Wolf
92e4b5aa77 Add writeback mode to "sim" command 2017-08-17 15:54:51 +02:00
Clifford Wolf
7b4f3f86c3 Improve "sim" command 2017-08-17 12:27:08 +02:00
Clifford Wolf
864498527a Merge pull request #386 from azonenberg/gpak-counters 
Bug fixes to GP_COUNTx and GP_PGEN cells in GreenPAK technology library
 2017-08-16 15:58:29 +02:00
Clifford Wolf
75046aa531 Add "sim" command skeleton 2017-08-16 13:05:21 +02:00
Andrew Zonenberg
e6eaf487b6 Fixed more issues with GreenPAK counter sim models 2017-08-15 09:18:36 -07:00
Andrew Zonenberg
3a404be62a Updated PGEN model to have level triggered reset (matches actual hardware behavior 2017-08-15 09:18:27 -07:00
Andrew Zonenberg
e5109847c9 Fixed bug in GP_COUNTx model 2017-08-15 09:18:17 -07:00
Andrew Zonenberg
66b256d40e Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high 2017-08-15 09:18:07 -07:00
Clifford Wolf
e9918365fd Merge branch 'azonenberg-rmports' 2017-08-15 11:32:55 +02:00
Clifford Wolf
88983f5012 Mostly coding style related fixes in rmports pass 2017-08-15 11:32:35 +02:00
Clifford Wolf
9fe6bc48a9 Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg-rmports 2017-08-15 11:19:55 +02:00
Clifford Wolf
2cf0b5c157 Merge pull request #381 from azonenberg/countfix 
Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
 2017-08-14 21:47:26 +02:00
Clifford Wolf
6d371f06ab Merge pull request #383 from azonenberg/abcfnames 
abc: Allow +/ filenames in the abc command
 2017-08-14 21:46:17 +02:00
Clifford Wolf
76efbcc15f Merge pull request #382 from azonenberg/jsoniofix 
json: Parse inout correctly rather than as an output
 2017-08-14 21:45:54 +02:00
Clifford Wolf
237b482b92 Merge pull request #384 from azonenberg/crtechlib 
CoolRunner-II technology library improvements
 2017-08-14 21:45:29 +02:00
Robert Ou
78fd24f40f coolrunner2: Add INVERT parameter to some BUFGs 2017-08-14 12:13:33 -07:00
Robert Ou
1e3ffd57cb coolrunner2: Add FFs with clock enable to cells_sim.v 2017-08-14 12:13:25 -07:00
Robert Ou
9a64ba3338 abc: Allow +/ filenames in the abc command 2017-08-14 12:11:11 -07:00
Robert Ou
366ce87cff json: Parse inout correctly rather than as an output 2017-08-14 12:09:03 -07:00
Andrew Zonenberg
15e41d6363 rmports: Now remove ports from cell instances if we optimized them out of that cell 2017-08-14 11:44:05 -07:00
Andrew Zonenberg
0ee27d0226 ProcessModule is no longer virtual (why was it in the first place?) 2017-08-14 11:18:09 -07:00
Andrew Zonenberg
bd2ac68769 rmports now works on all modules in the design, not just the top. 2017-08-14 11:16:44 -07:00
Andrew Zonenberg
d5e5bbad86 Updated Makefile to reflect opt_rmports being renamed to rmports 2017-08-14 11:04:56 -07:00
Andrew Zonenberg
1a6a23f91a Renamed opt_rmports pass to rmports 2017-08-14 11:00:45 -07:00
Andrew Zonenberg
348acbd968 Fixed typo in GP_COUNT8 sim model 2017-08-14 10:45:40 -07:00
Andrew Zonenberg
c205d571df Fixed typo in error message 2017-08-14 10:45:40 -07:00
Andrew Zonenberg
0a6c702c41 Changed LEVEL resets for GP_COUNTx to be properly synthesizeable 2017-08-14 10:45:40 -07:00
Andrew Zonenberg
9f3dc59ffe Changed LEVEL resets to be edge triggered anyway 2017-08-14 10:45:40 -07:00
Andrew Zonenberg
b049ead042 Added level-triggered reset support to GP_COUNTx simulation models 2017-08-14 10:45:40 -07:00
Andrew Zonenberg
ac75524f69 Fixed undeclared "count" in GP_COUNT8_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg
db20e3f1c2 Fixed undeclared "count" in GP_COUNT14_ADV 2017-08-14 10:45:39 -07:00
Andrew Zonenberg
3618ca2218 Fixed typo in last commit 2017-08-14 10:45:39 -07:00
Andrew Zonenberg
4da1a327c0 Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock divide, but do everything else. 2017-08-14 10:45:39 -07:00