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https://github.com/YosysHQ/yosys
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Further improve extract_fa (seems to be fully functional now)
This commit is contained in:
Clifford Wolf
parent
0bf612506c
commit
382cc90c65
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@ -54,12 +54,26 @@ struct ExtractFaWorker
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dict<SigBit, Cell*> driver;
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pool<SigBit> handled_bits;
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const int xor2_func = 0x6, xnor2_func = 0x9;
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const int xor3_func = 0x96, xnor3_func = 0x69;
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pool<tuple<SigBit, SigBit>> xorxnor2;
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pool<tuple<SigBit, SigBit, SigBit>> xorxnor3;
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dict<tuple<SigBit, SigBit>, dict<int, pool<SigBit>>> func2;
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dict<tuple<SigBit, SigBit, SigBit>, dict<int, pool<SigBit>>> func3;
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struct func2_and_info_t {
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bool inv_a, inv_b, inv_y;
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};
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struct func3_maj_info_t {
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bool inv_a, inv_b, inv_c, inv_y;
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};
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dict<int, func2_and_info_t> func2_and_info;
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dict<int, func3_maj_info_t> func3_maj_info;
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ExtractFaWorker(const ExtractFaConfig &config, Module *module) :
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config(config), module(module), ce(module), sigmap(ce.assign_map)
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{
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@ -74,11 +88,68 @@ struct ExtractFaWorker
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driver[y] = cell;
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}
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}
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for (int ia = 0; ia < 2; ia++)
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for (int ib = 0; ib < 2; ib++)
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{
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func2_and_info_t f2i;
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f2i.inv_a = ia;
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f2i.inv_b = ib;
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f2i.inv_y = false;
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int func = 0;
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for (int i = 0; i < 4; i++)
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{
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bool a = (i & 1) ? !f2i.inv_a : f2i.inv_a;
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bool b = (i & 2) ? !f2i.inv_b : f2i.inv_b;
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if (a && b) func |= 1 << i;
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}
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log_assert(func2_and_info.count(func) == 0);
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func2_and_info[func] = f2i;
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f2i.inv_y = true;
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func ^= 15;
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log_assert(func2_and_info.count(func) == 0);
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func2_and_info[func] = f2i;
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}
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for (int ia = 0; ia < 2; ia++)
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for (int ib = 0; ib < 2; ib++)
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for (int ic = 0; ic < 2; ic++)
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{
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func3_maj_info_t f3i;
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f3i.inv_a = ia;
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f3i.inv_b = ib;
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f3i.inv_c = ic;
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f3i.inv_y = false;
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int func = 0;
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for (int i = 0; i < 8; i++)
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{
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bool a = (i & 1) ? !f3i.inv_a : f3i.inv_a;
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bool b = (i & 2) ? !f3i.inv_b : f3i.inv_b;
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bool c = (i & 4) ? !f3i.inv_c : f3i.inv_c;
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if ((a && b) || (a && c) || (b &&c)) func |= 1 << i;
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}
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log_assert(func3_maj_info.count(func) == 0);
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func3_maj_info[func] = f3i;
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// f3i.inv_y = true;
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// func ^= 255;
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// log_assert(func3_maj_info.count(func) == 0);
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// func3_maj_info[func] = f3i;
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}
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}
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void check_partition(SigBit root, pool<SigBit> &leaves)
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{
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if (GetSize(leaves) == 2)
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if (config.enable_ha && GetSize(leaves) == 2)
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{
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leaves.sort();
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@ -108,13 +179,13 @@ struct ExtractFaWorker
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// log("%04d %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(root));
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if (func == 0x6 || func == 0x9)
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if (func == xor2_func || func == xnor2_func)
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xorxnor2.insert(tuple<SigBit, SigBit>(A, B));
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func2[tuple<SigBit, SigBit>(A, B)][func].insert(root);
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}
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if (GetSize(leaves) == 3)
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if (config.enable_fa && GetSize(leaves) == 3)
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{
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leaves.sort();
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@ -147,7 +218,7 @@ struct ExtractFaWorker
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// log("%08d %s %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(C), log_signal(root));
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if (func == 0x69 || func == 0x96)
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if (func == xor3_func || func == xnor3_func)
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xorxnor3.insert(tuple<SigBit, SigBit, SigBit>(A, B, C));
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func3[tuple<SigBit, SigBit, SigBit>(A, B, C)][func].insert(root);
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@ -159,6 +230,11 @@ struct ExtractFaWorker
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if (cache.count(leaves))
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return;
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// log("%*s[%d] %s:", 20-maxdepth, "", maxdepth, log_signal(root));
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// for (auto bit : leaves)
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// log(" %s", log_signal(bit));
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// log("\n");
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cache.insert(leaves);
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check_partition(root, leaves);
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@ -186,15 +262,29 @@ struct ExtractFaWorker
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}
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}
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void assign_new_driver(SigBit bit, SigBit new_driver)
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{
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Cell *cell = driver.at(bit);
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if (sigmap(cell->getPort("\\Y")) == bit) {
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cell->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, new_driver);
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}
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}
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void run()
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{
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log("Extracting full/half adders from %s:\n", log_id(module));
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for (auto it : driver)
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{
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if (it.second->type.in("$_BUF_", "$_NOT_"))
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continue;
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SigBit root = it.first;
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pool<SigBit> leaves = { root };
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pool<pool<SigBit>> cache;
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find_partitions(root, leaves, cache, 5, 10);
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find_partitions(root, leaves, cache, 20, 10);
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}
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for (auto &key : xorxnor3)
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@ -203,14 +293,81 @@ struct ExtractFaWorker
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SigBit B = get<1>(key);
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SigBit C = get<2>(key);
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log("3-Input XOR/XNOR %s %s %s:\n", log_signal(A), log_signal(B), log_signal(C));
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log(" 3-Input XOR/XNOR %s %s %s:\n", log_signal(A), log_signal(B), log_signal(C));
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for (auto &it : func3.at(key)) {
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log(" %08d ->", bindec(it.first));
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for (auto &it : func3.at(key))
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{
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if (it.first != xor3_func && it.first != xnor3_func)
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continue;
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log(" %08d ->", bindec(it.first));
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for (auto bit : it.second)
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log(" %s", log_signal(bit));
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log("\n");
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}
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for (auto &it : func3_maj_info)
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{
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int func = it.first;
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auto f3i = it.second;
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if (func3.at(key).count(func) == 0)
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continue;
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if (func3.at(key).count(xor3_func) == 0 && func3.at(key).count(xnor3_func) != 0) {
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f3i.inv_a = !f3i.inv_a;
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f3i.inv_b = !f3i.inv_b;
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f3i.inv_c = !f3i.inv_c;
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f3i.inv_y = !f3i.inv_y;
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}
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if (!f3i.inv_a && !f3i.inv_b && !f3i.inv_c && !f3i.inv_y) {
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log(" Majority without inversions:\n");
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} else {
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log(" Majority with inverted");
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if (f3i.inv_a) log(" A");
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if (f3i.inv_b) log(" B");
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if (f3i.inv_c) log(" C");
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if (f3i.inv_y) log(" Y");
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log(":\n");
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}
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log(" %08d ->", bindec(func));
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for (auto bit : func3.at(key).at(func))
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log(" %s", log_signal(bit));
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log("\n");
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Cell *cell = module->addCell(NEW_ID, "$fa");
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cell->setParam("\\WIDTH", 1);
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log(" Created $fa cell %s.\n", log_id(cell));
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cell->setPort("\\A", f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
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cell->setPort("\\B", f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
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cell->setPort("\\C", f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
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SigBit X = module->addWire(NEW_ID);
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SigBit Y = module->addWire(NEW_ID);
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cell->setPort("\\X", X);
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cell->setPort("\\Y", Y);
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if (func3.at(key).count(xor3_func)) {
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for (auto bit : func3.at(key).at(xor3_func))
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assign_new_driver(bit, Y);
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}
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if (func3.at(key).count(xnor3_func)) {
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SigBit YN = module->NotGate(NEW_ID, Y);
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for (auto bit : func3.at(key).at(xnor3_func))
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assign_new_driver(bit, YN);
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}
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SigBit XX = f3i.inv_y ? module->NotGate(NEW_ID, X) : X;
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for (auto bit : func3.at(key).at(func))
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assign_new_driver(bit, XX);
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}
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}
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for (auto &key : xorxnor2)
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@ -218,14 +375,73 @@ struct ExtractFaWorker
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SigBit A = get<0>(key);
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SigBit B = get<1>(key);
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log("2-Input XOR/XNOR %s %s:\n", log_signal(A), log_signal(B));
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log(" 2-Input XOR/XNOR %s %s:\n", log_signal(A), log_signal(B));
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for (auto &it : func2.at(key))
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{
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if (it.first != xor2_func && it.first != xnor2_func)
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continue;
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for (auto &it : func2.at(key)) {
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log(" %04d ->", bindec(it.first));
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for (auto bit : it.second)
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log(" %s", log_signal(bit));
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log("\n");
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}
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for (auto &it : func2_and_info)
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{
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int func = it.first;
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auto &f2i = it.second;
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if (func2.at(key).count(func) == 0)
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continue;
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if (!f2i.inv_a && !f2i.inv_b && !f2i.inv_y) {
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log(" AND without inversions:\n");
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} else {
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log(" AND with inverted");
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if (f2i.inv_a) log(" A");
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if (f2i.inv_b) log(" B");
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if (f2i.inv_y) log(" Y");
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log(":\n");
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}
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log(" %04d ->", bindec(func));
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for (auto bit : func2.at(key).at(func))
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log(" %s", log_signal(bit));
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log("\n");
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Cell *cell = module->addCell(NEW_ID, "$fa");
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cell->setParam("\\WIDTH", 1);
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log(" Created $fa cell %s.\n", log_id(cell));
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cell->setPort("\\A", f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
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cell->setPort("\\B", f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
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cell->setPort("\\C", State::S0);
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SigBit X = module->addWire(NEW_ID);
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SigBit Y = module->addWire(NEW_ID);
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cell->setPort("\\X", X);
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cell->setPort("\\Y", Y);
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if (func2.at(key).count(xor2_func)) {
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for (auto bit : func2.at(key).at(xor2_func))
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assign_new_driver(bit, Y);
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}
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if (func2.at(key).count(xnor2_func)) {
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SigBit YN = module->NotGate(NEW_ID, Y);
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for (auto bit : func2.at(key).at(xnor2_func))
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assign_new_driver(bit, YN);
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}
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SigBit XX = f2i.inv_y ? module->NotGate(NEW_ID, X) : X;
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for (auto bit : func2.at(key).at(func))
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assign_new_driver(bit, XX);
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}
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}
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}
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};
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