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Author	SHA1	Message	Date
Eddie Hung	26657037b8	Update doc with max cascade chain of 20	2019-09-26 14:31:02 -07:00
Eddie Hung	5b9deef10d	Do not always zero out C (e.g. during cascade breaks)	2019-09-26 13:59:05 -07:00
Eddie Hung	95f0dd57df	Update doc	2019-09-26 13:44:41 -07:00
Eddie Hung	58f31096ab	Zero out ports	2019-09-26 13:40:38 -07:00
Eddie Hung	af59856ba1	xilinx_dsp_cascade to also cascade AREG and BREG	2019-09-26 13:29:18 -07:00
Eddie Hung	832216dab0	Try recursive pmgen for P cascade	2019-09-26 12:09:57 -07:00
Eddie Hung	143f82def2	Missing an '&'	2019-09-26 11:13:08 -07:00
Eddie Hung	84825f9378	Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once	2019-09-26 10:45:14 -07:00
Miodrag Milanovic	435300f930	Make read/write gzip files on macos works, fixes #1357	2019-09-26 19:35:12 +02:00
Eddie Hung	033aefc0f4	Typo	2019-09-26 10:34:14 -07:00
Eddie Hung	bd8661e024	CREG to check for \keep	2019-09-26 10:32:01 -07:00
Eddie Hung	c0bb1d22e8	Remove newline	2019-09-26 10:31:55 -07:00
Eddie Hung	781dda6175	select once	2019-09-26 10:15:05 -07:00
Eddie Hung	27e5bf5aad	Stop trying to be too smart by prematurely optimising	2019-09-26 09:57:11 -07:00
Eddie Hung	35aaa8d73a	mul2dsp.v slice names	2019-09-25 22:58:55 -07:00
Eddie Hung	f1de93edf5	Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)	2019-09-25 22:58:03 -07:00
Eddie Hung	cd8a640989	Reject if (* init *) present	2019-09-25 18:21:08 -07:00
Eddie Hung	34aa3532fb	Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit	2019-09-25 17:26:47 -07:00
Eddie Hung	a4238637ac	Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" ... This reverts commit 234738b103.	2019-09-25 17:25:44 -07:00
Eddie Hung	f4387e817c	Revert "No need for $__mul anymore?" ... This reverts commit 1d875ac76a.	2019-09-25 17:24:11 -07:00
Eddie Hung	aeb1539818	Rework xilinx_dsp postAdd for new wreduce call	2019-09-25 17:22:30 -07:00
Eddie Hung	63940913d2	Only wreduce on t:$add	2019-09-25 17:22:04 -07:00
Eddie Hung	234738b103	Remove _TECHMAP_CELLTYPE_ check since all $mul	2019-09-25 16:51:31 -07:00
Eddie Hung	5f8917c984	Fix memory issue since SigSpec& could be invalidated	2019-09-25 16:45:51 -07:00
Eddie Hung	a009314597	Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40 ... ICE40 tests. adffs test update (equiv_opt -multiclock).	2019-09-25 16:43:24 -07:00
Eddie Hung	1d875ac76a	No need for $__mul anymore?	2019-09-25 14:06:21 -07:00
Eddie Hung	486dd7c483	unextend only used in init	2019-09-25 14:05:59 -07:00
Eddie Hung	53ea5daa42	Call 'wreduce' after mul2dsp to avoid unextend()	2019-09-25 14:04:36 -07:00
Eddie Hung	93363c94a2	Oops. Actually use __NAME__ in ABC_DSP48E1 macro	2019-09-25 10:33:16 -07:00
SergeyDegtyar	b66364ada2	Change sync controls to async.	2019-09-25 14:43:26 +03:00
Clifford Wolf	739c621330	Merge pull request #1402 from YosysHQ/clifford/portlist ... Add "portlist" command	2019-09-25 09:20:54 +02:00
Clifford Wolf	b432c9b44b	Improve "portlist" command ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-09-25 09:20:38 +02:00
Clifford Wolf	6c427d36dd	Add "portlist" command ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-09-24 18:08:59 +02:00
SergeyDegtyar	fc6ebf8268	adffs test update (equiv_opt -multiclock).	2019-09-24 14:55:32 +03:00
Eddie Hung	b41d2fb4e4	Add (* techmap_autopurge *) to abc_unmap.v too	2019-09-23 22:02:22 -07:00
Eddie Hung	44374b1b2b	"abc_padding" attr for blackbox outputs that were padded, remove them later	2019-09-23 21:58:40 -07:00
Eddie Hung	c340fbfab2	Force $inout.out ports to begin with '$' to indicate internal	2019-09-23 21:58:04 -07:00
Eddie Hung	11ac37733d	Add techmap_autopurge to outputs in abc_map.v too	2019-09-23 21:56:28 -07:00
Eddie Hung	27167848f4	Revert "Add a xilinx_finalise pass" ... This reverts commit 23d90e0439.	2019-09-23 19:52:55 -07:00
Eddie Hung	0f53893104	Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" ... This reverts commit 67c2db3486.	2019-09-23 19:52:55 -07:00
Eddie Hung	29db96fa1f	Revert "Vivado does not like zero width port connections" ... This reverts commit 895e2befa7.	2019-09-23 19:52:54 -07:00
Eddie Hung	895e2befa7	Vivado does not like zero width port connections	2019-09-23 19:04:07 -07:00
Eddie Hung	67c2db3486	Remove (* techmap_autopurge *) from abc_unmap.v since no effect	2019-09-23 18:56:18 -07:00
Eddie Hung	23d90e0439	Add a xilinx_finalise pass	2019-09-23 18:56:02 -07:00
Eddie Hung	e556d48d45	Set [AB]CASCREG to legal values	2019-09-23 16:00:11 -07:00
Eddie Hung	b824a56cde	Comment to explain separating CREG packing	2019-09-23 13:58:10 -07:00
Eddie Hung	15dfbc8125	Separate out CREG packing into new pattern, to avoid conflict with PREG	2019-09-23 13:27:10 -07:00
Eddie Hung	26a6c55665	Move log_debug("\n") later	2019-09-23 13:27:00 -07:00
Eddie Hung	d0dbbc2605	Move unextend initialisation later	2019-09-23 13:26:34 -07:00
Eddie Hung	a67af3d5e5	Use new port() overload once more	2019-09-23 13:00:44 -07:00