Eddie Hung
f3e150d9a5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 09:21:51 -07:00
Miodrag Milanović
ce0631c371
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out
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Support binary files for backends, fixes #1407
2019-09-29 10:37:34 +02:00
Clifford Wolf
178c67ea22
Merge pull request #1411 from aman-goel/YosysHQ-master
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Corrects BTOR2 backend
2019-09-29 10:36:25 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Miodrag Milanovic
0c380f0855
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
Miodrag Milanovic
d0493925ec
Support binary files for backends, fixes #1407
2019-09-28 09:36:18 +02:00
Eddie Hung
c372e7baf9
Fix box name
2019-09-27 18:49:45 -07:00
Eddie Hung
cfa6dd61ef
Use abc_mergeability attr for "r" extension
2019-09-27 18:41:43 -07:00
Eddie Hung
313d2478e9
Split ABC9 based on clocking only, add "abc_mergeability" attr for en
2019-09-27 18:41:04 -07:00
Eddie Hung
dc154c39a8
Fix infinite recursion
2019-09-27 17:45:49 -07:00
Eddie Hung
fe722b737c
Add -select option to aigmap
2019-09-27 17:44:01 -07:00
Eddie Hung
11cb5fab00
Fix typo
2019-09-27 17:00:19 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Aman Goel
5eebfabe42
Corrects btor2 backend
2019-09-27 12:40:17 -04:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
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Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Aman Goel
cb0dc6e68b
Merge pull request #7 from YosysHQ/master
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Syncing with official repo
2019-09-27 12:30:27 -04:00
Miodrag Milanović
4b15cf5f76
Merge pull request #1409 from YosysHQ/mmicko/fix_getopt_difference
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Change order of parameters, to work on other OS
2019-09-27 17:37:55 +02:00
Miodrag Milanovic
7f0eec8270
Change order of parameters, to work on other os
2019-09-27 11:31:55 +02:00
Clifford Wolf
7bde555481
Merge pull request #1404 from YosysHQ/fix_gzip_macos
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Make read/write gzip files on macos works, fixes #1357
2019-09-27 09:57:28 +02:00
Eddie Hung
143f82def2
Missing an '&'
2019-09-26 11:13:08 -07:00
Miodrag Milanovic
435300f930
Make read/write gzip files on macos works, fixes #1357
2019-09-26 19:35:12 +02:00
Eddie Hung
a009314597
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40
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ICE40 tests. adffs test update (equiv_opt -multiclock).
2019-09-25 16:43:24 -07:00
SergeyDegtyar
b66364ada2
Change sync controls to async.
2019-09-25 14:43:26 +03:00
Clifford Wolf
739c621330
Merge pull request #1402 from YosysHQ/clifford/portlist
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Add "portlist" command
2019-09-25 09:20:54 +02:00
Clifford Wolf
b432c9b44b
Improve "portlist" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-25 09:20:38 +02:00
Clifford Wolf
6c427d36dd
Add "portlist" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-24 18:08:59 +02:00
SergeyDegtyar
fc6ebf8268
adffs test update (equiv_opt -multiclock).
2019-09-24 14:55:32 +03:00
Miodrag Milanović
057dae4f78
Merge pull request #1399 from nakengelhardt/fix-show-macos
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fix show command for macos
2019-09-23 20:06:40 +02:00
N. Engelhardt
2b81ce5648
add xdot dependency to Brewfile
2019-09-23 18:25:04 +02:00
N. Engelhardt
3bed4cb18a
fix show command for macos
2019-09-23 17:47:05 +02:00
Clifford Wolf
0a2d8db793
Merge pull request #1392 from YosysHQ/eddie/fix1391
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(* techmap_autopurge *) fixes when ports aren't consistently-sized
2019-09-21 11:25:36 +02:00
Eddie Hung
7c8de1dd18
Hell let's add the original #1381 testcase too
2019-09-20 17:58:51 -07:00
Eddie Hung
ec08a031b5
Revert abc9.cc
2019-09-20 17:52:23 -07:00
Eddie Hung
6258e6a7e2
Add testcase
2019-09-20 17:51:45 -07:00
Eddie Hung
72ce06909e
Trim mismatched connection to be same (smallest) size
2019-09-20 17:51:36 -07:00
Eddie Hung
567e5f0aa7
Fix first testcase in #1391
2019-09-20 17:51:27 -07:00
Clifford Wolf
f3781f98db
Merge pull request #1386 from YosysHQ/clifford/fix1360
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Fix handling of read_verilog config in AstModule::reprocess_module()
2019-09-20 13:30:28 +02:00
Clifford Wolf
8da0888bf6
Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 12:16:20 +02:00
Clifford Wolf
c072e00a39
Update CHANGELOG
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 10:28:20 +02:00
Clifford Wolf
1f64b34c64
Add "add -mod"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 10:27:17 +02:00
Clifford Wolf
db17833a5f
Merge pull request #1384 from YosysHQ/clifford/fix1381
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Add techmap_autopurge attribute
2019-09-20 09:58:42 +02:00
Clifford Wolf
b76fac3ac3
Add techmap_autopurge attribute, fixes #1381
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-19 20:00:52 +02:00
Marcin Kościelnicki
13fa873f11
Use extractinv for synth_xilinx -ise
2019-09-19 04:02:48 +02:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Eddie Hung
70c607d7dd
Document (* gentb_skip *) attr for test_autotb
2019-09-18 12:41:35 -07:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
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peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
Eddie Hung
3ec28ec53a
Merge pull request #1379 from mmicko/sim_models
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Added simulation models for Efinix and Anlogic
2019-09-18 10:04:27 -07:00
Miodrag Milanovic
3e9449cb0b
make note that it is for latch mode
2019-09-18 17:48:16 +02:00
Miodrag Milanovic
b0ca6de472
better lut handling
2019-09-18 17:45:19 +02:00
Miodrag Milanovic
8badd4d812
better handling of lut and begin/end add
2019-09-18 17:45:07 +02:00
