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17464 commits 134 branches 69 tags 58 MiB
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37 commits

Author SHA1 Message Date
Lofty
75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 
Move rename logic to abc_ops_reintegrate
 2026-07-09 08:46:46 +00:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Lofty
091d2a7814 Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
Miodrag Milanovic
7fe32137bd Revert "Fix tests due to ABC improvements" 
This reverts commit 417e871b06.
 2026-05-11 14:47:08 +02:00
Miodrag Milanovic
ced2521b03 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
Miodrag Milanovic
417e871b06 Fix tests due to ABC improvements 2026-03-30 15:23:27 +01:00
Robert O'Callahan
8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Emil J. Tywoniak
6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
Lofty
8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
Miodrag Milanovic
e6f7cf3b29 Update tests 2023-06-09 14:41:45 +02:00
Lofty
00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
KrystalDelusion
8f6a06951c Fix for sync_ram_sdp not being final module 
Explicitly declare -top in synth_intel_alm.
 2023-02-21 05:23:16 +13:00
Jannis Harder
0113f44faa Reenable existing equiv_opt tests 2022-10-07 16:04:51 +02:00
Lofty
9f7a55c99f intel_alm: M10K write-enable is negative-true 2022-03-09 20:18:06 +00:00
Marcelina Kościelnicka
18806f1ef6 memory_bram: Reuse extract_rdff helper for make_outreg. 
Also properly skip read ports with init value or reset when not making
use of make_outreg.  Proper support for matching those will land later.
 2021-05-25 22:42:03 +02:00
gatecat
34a08750fa intel_alm: Fix illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat
eb106732d9 intel_alm: Add global buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat
5dba138c87 intel_alm: Add IO buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
Xiretza
acd47bbd52
tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
Dan Ravensloft
1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
 2020-08-26 22:50:16 +02:00
Marcelina Kościelnicka
50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path. 
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
 2020-08-20 12:44:09 +02:00
Marcelina Kościelnicka
9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Dan Ravensloft
a2fb84fd0c intel_alm: direct M10K instantiation 
This reverts commit a3a90f6377.
 2020-07-27 15:39:06 +02:00
Dan Ravensloft
62311b7ec0 intel_alm: increase abc9 -W 2020-07-26 23:56:54 +02:00
Dan Ravensloft
4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Lofty
a3a90f6377 Revert "intel_alm: direct M10K instantiation" 
This reverts commit 09ecb9b2cf.
 2020-07-13 18:05:38 +02:00
Dan Ravensloft
09ecb9b2cf intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
Dan Ravensloft
0d4c2f0a65 intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
Dan Ravensloft
b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
3ca2de0f77 synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
Dan Ravensloft
c6765443fd Improve MISTRAL_FF specify rules 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2020-07-04 19:45:10 +02:00
Eddie Hung
52fbaeca07 tests: update fsm.ys resource count 
Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862?
 2020-07-04 19:45:10 +02:00
Dan Ravensloft
8b4eb78849 intel_alm: fix DFFE matching 2020-06-11 19:55:51 +02:00
Claire Wolf
7112f187cd Add missing .gitignore file 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 22:25:47 +02:00
Dan Ravensloft
5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00
Dan Ravensloft
3d149aff73 intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
Dan Ravensloft
2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00