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Code Activity
16055 commits 122 branches 59 tags 71 MiB
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248 commits

Author SHA1 Message Date
Krystine Sherwin
f32d6429bd memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2025-10-18 12:12:25 +01:00
Robert O'Callahan
1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Robert O'Callahan
a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan
23f196a3b8 Update passes/memory to avoid bits() 2025-09-16 03:17:23 +00:00
Jannis Harder
dd9627ed05
Merge pull request #5336 from rocallahan/remove-log-cstr 
Remove `.c_str()` calls from `log()`/`log_error()`
 2025-09-12 14:09:48 +02:00
Krystine Sherwin
f102b25914 Reapply "Merge pull request #5301 from KrystalDelusion/krys/re_5280" 
This reverts commit 88eb83a0c3.
 2025-09-12 10:41:01 +02:00
Robert O'Callahan
e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Jannis Harder
61a00b9131 memory_libmap: Fix use of uninitialized value for async read ports 
The code in memory_libmap expects `clk_en` to be initialized for all
`PortVariant`s but the parsing in memlib.cc didn't initialize it for
variants of kind `PortKind::Ar` (async read ports).

While this fixes the immediate CI failure, it would be best to refactor
the code so it becomes obvious if something isn't initialized.
 2025-09-09 13:32:46 +02:00
Robert O'Callahan
c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Miodrag Milanovic
88eb83a0c3 Revert "Merge pull request #5301 from KrystalDelusion/krys/re_5280" 
This reverts commit c9a602e882, reversing
changes made to 51eaaffe09.
 2025-08-28 11:58:02 +02:00
Krystine Sherwin
3ca2b7951f
memlib: Fix ubsan 2025-08-19 17:05:51 +12:00
Emil J. Tywoniak
c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
Fred Tombs
b64484795d Fix typos in memlib 2025-07-29 15:27:59 -04:00
Emil J. Tywoniak
872a197e94 memory_libmap: fix MapWorker memory allocation 2025-04-14 12:41:14 +02:00
Emil J. Tywoniak
55b60dca95 memory_libmap: update indices on design modification 2025-02-11 13:32:34 +01:00
Emil J. Tywoniak
785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Martin Povišer
158fbf881e memory_map: Explain -iattr better 2024-03-06 15:15:37 +01:00
Martin Povišer
030d639201 opt_mem, memory_*: Refuse to operate in presence of processes 
Processes can contain `MemWriteAction` entries which are invisible to
most passes operating on memories but which will be lowered to write
ports later on by `proc_memwr`. For that reason we can get corrupted
RTLIL if we sequence the memory passes before `proc`. Address that by
making the affected memory passes ignore modules with processes.
 2024-02-23 12:27:53 +01:00
Martin Povišer
975517b022 memory_memx: Fix log header 2024-02-23 12:27:10 +01:00
uis
5902b2826d Fix printf formats 2024-01-15 12:07:54 +01:00
N. Engelhardt
080da693d1 memory_libmap: update search order for attributes 2023-10-24 13:55:45 +02:00
N. Engelhardt
1b6d1e9419 memory_libmap: look for ram_style attributes on surrounding signals 2023-10-19 19:23:35 +02:00
Martin Povišer
c6566b660f memlib.md: Fix typo 2023-09-04 17:38:35 +02:00
Martin Povišer
3de84b959f memory_libmap: Tweak whitespace 2023-09-04 17:38:35 +02:00
N. Engelhardt
57de249881 memory_libmap: print additional debug messages when no valid mapping is found 2023-07-06 18:54:32 +02:00
N. Engelhardt
a6be7b4751 memory_libmap: add debug messages for some reasons for rejecting mappings 2023-06-29 14:08:31 +02:00
N. Engelhardt
7542146fc5 memory_libmap: print message about attributes forcing ram kind 2023-06-28 17:48:20 +02:00
KrystalDelusion
9465b2af95 Fitting help messages to 80 character width 
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
 2022-08-24 10:40:57 +12:00
Jannis Harder
a2f9ebe43a memory_map: Add -formal option 
This maps memories for a global clock based formal verification flow.
This implies -keepdc, uses $ff cells for ROMs and sets hdlname
attributes.
 2022-08-16 13:37:30 +02:00
Jannis Harder
a6b440b5c9 memory_map: avoid undriven unused FF inputs for -keepdc 2022-06-28 19:05:35 +02:00
Jannis Harder
d78d807a7f memory_map: -keepdc option for formal 
Use it when invoking memory_map -rom-only from write_{smt2,btor}.
 2022-06-27 15:47:55 +02:00
Marcelina Kościelnicka
ab3a9325c3 memory_map: Add -rom-only option. 2022-06-17 16:56:11 +02:00
Marcelina Kościelnicka
01daa077a2 memory_map: Use const drivers instead of FFs for ROMs. 2022-06-17 15:17:14 +02:00
Marcelina Kościelnicka
d69091806a memory_libmap: Fix wrprio handling. 2022-06-17 02:09:37 +02:00
Marcelina Kościelnicka
25a4cd7020 memory_libmap: Fix params emitted for unused ports for consistency. 2022-06-16 08:14:08 +02:00
Marcelina Kościelnicka
71dfbf33b2 Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. 2022-06-02 23:16:12 +02:00
Marcelina Kościelnicka
3a0aa9c663 memory_dff: Add support for no_rw_check attribute. 2022-06-02 12:49:34 +02:00
Marcelina Kościelnicka
606f1637ae Add memory_bmux2rom pass. 2022-05-18 22:48:55 +02:00
Marcelina Kościelnicka
7c5dba8b77 Add memory_libmap pass. 2022-05-18 17:32:56 +02:00
imhcyx
71166eeecf memory_share: fix wrong argidx in extra_args 2022-05-05 16:58:39 +08:00
Marcelina Kościelnicka
25ff83f0b5 memory_share: Fix up mismatched address widths. 2022-04-15 22:01:00 +02:00
Marcelina Kościelnicka
1759c80a3f memory_bram: Make use of new mem emulation functions to map more RAMs. 2022-01-27 19:31:27 +01:00
Marcelina Kościelnicka
f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports. 
Fixes #3117.
 2021-12-20 18:40:14 +01:00
Marcelina Kościelnicka
4e70c30775 FfData: some refactoring. 
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
 2021-10-07 04:24:06 +02:00
Marcelina Kościelnicka
63b9df8693 kernel/ff: Refactor FfData to enable FFs with async load. 
- *_en is split into *_ce (clock enable) and *_aload (async load aka
  latch gate enable), so both can be present at once
- has_d is removed
- has_gclk is added (to have a clear marker for $ff)
- d_is_const and val_d leftovers are removed
- async2sync, clk2fflogic, opt_dff are updated to operate correctly on
  FFs with async load
 2021-10-02 20:19:48 +02:00
Marcelina Kościelnicka
f791328506 Add opt_mem_widen pass. 
If all of us are wide, then none of us are!
 2021-08-14 01:06:23 +02:00
Marcelina Kościelnicka
1f74ec3535 memory_share: Add -nosat and -nowiden options. 
This unlocks wide port recognition by default.
 2021-08-14 00:09:04 +02:00
Marcelina Kościelnicka
9fdedf4d1c memory_dff: Recognize soft transparency logic. 2021-08-13 23:08:32 +02:00
Marcelina Kościelnicka
616ace2d92 Add new opt_mem_priority pass. 2021-08-13 11:58:52 +02:00
Marcelina Kościelnicka
d0d9aca2c3 memory_share: Pass addresses through sigmap_xmux everywhere. 
This fixes wide port recognition in some cases.
 2021-08-13 01:17:55 +02:00