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16055 commits 121 branches 59 tags 69 MiB
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Author SHA1 Message Date
Krystine Sherwin
f2b88c23d4 analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2025-10-18 12:14:03 +01:00
Krystine Sherwin
6e5524ee9c analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2025-10-18 12:14:01 +01:00
Krystine Sherwin
f32d6429bd memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2025-10-18 12:12:25 +01:00
Lofty
a119711aac analogdevices: LUT RAM only on positive edge 2025-10-18 12:11:18 +01:00
Lofty
f1579304a6 analogdevices: DSP tweaks 2025-10-18 12:10:50 +01:00
Lofty
059925a56a analogdevices: DSP inference 2025-10-16 23:33:59 +01:00
Lofty
aab52403f1 analogdevices: remove cells_xtra 2025-10-16 09:27:15 +01:00
Lofty
d43f6f7274 analogdevices: timings for t40lp 2025-10-16 08:43:08 +01:00
Lofty
6d0c2fe048 analogdevices: use single tech param 2025-10-16 08:43:08 +01:00
Lofty
7e894d4159 analogdevices: expreso does not care about clock buffers 2025-10-16 08:43:08 +01:00
Lofty
9cfa5fb369 analogdevices: prepare for t40lp timings 2025-10-16 08:43:08 +01:00
Krystine Sherwin
151f530677 analogdevices: Adding RBRAM2 and -tech 2025-10-16 08:43:08 +01:00
Krystine Sherwin
edeb6128ab analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2025-10-16 08:43:08 +01:00
Krystine Sherwin
55040dc6b1 analogdevices: Update lutram.ys test 2025-10-16 08:43:08 +01:00
Krystine Sherwin
18a4e44b28 analogdevices: Native LUTRAM primitives 2025-10-16 08:43:08 +01:00
Lofty
b3e3614c96 analogdevices: LUTRAM config 2025-10-16 08:43:08 +01:00
Lofty
0bec90930f analogdevices: update timing model 2025-10-16 08:43:08 +01:00
Lofty
9c8a563305 I thought I removed this... 2025-10-16 08:43:08 +01:00
Lofty
b8254b96c7 analogdevices: user retargeting 2025-10-16 08:43:08 +01:00
Lofty
799a4e4291 analogdevices: more housekeeping 2025-10-16 08:43:08 +01:00
Lofty
c7580131ad analogdevices: remove some extra cells! 2025-10-16 08:43:08 +01:00
Lofty
2cdd97a8d4 test suite 2025-10-16 08:43:08 +01:00
Lofty
04fd4d4601 synth_analogdevices: remove scopeinfo cells 2025-10-16 08:43:08 +01:00
Lofty
7878a7e2bd Create synth_analogdevices 2025-10-16 08:43:08 +01:00
Miodrag Milanovic
db8c1878a0 fix dlopen using fs:path with mingw 2025-10-16 08:30:43 +02:00
github-actions[bot]
061b6ce2ad Bump version 2025-10-16 00:23:57 +00:00
Miodrag Milanović
759996b968
Merge pull request #5427 from donn/plugin_search_paths 
plugins: add search paths
 2025-10-15 20:02:05 +02:00
Emil J
9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec 
Don't stop parsing sigspec after a {} group.
 2025-10-15 17:31:11 +02:00
Mohamed Gaber
dce70abd94
plugins: support Windows path delimiters 2025-10-15 15:53:44 +03:00
Mohamed Gaber
e86797f029
plugins: add search path 
This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules.

This addresses https://github.com/YosysHQ/yosys/issues/2545, allowing Yosys to be better packaged in non-FHS environments such as Nix.
 2025-10-15 14:13:25 +03:00
github-actions[bot]
4970ad5a18 Bump version 2025-10-15 00:23:49 +00:00
Robert O'Callahan
e099a7d34a Don't stop parsing sigspec after a {} group. 
Resolves #5424
 2025-10-14 21:18:58 +00:00
Miodrag Milanović
2e3bfca294
Merge pull request #5419 from YosysHQ/micko/verific_fix_nocolumns 
verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
 2025-10-14 17:05:31 +02:00
Miodrag Milanović
a89c5b97d8
Merge pull request #5423 from YosysHQ/update_abc 
Update abc
 2025-10-14 17:05:13 +02:00
Emil J
a5960ce515
Merge pull request #5197 from YosysHQ/emil/opensta-verilog-export 
OpenSTA verilog compatibility
 2025-10-14 16:46:37 +02:00
Miodrag Milanovic
7d2857b30f Fix regex checks 2025-10-14 16:04:56 +02:00
N. Engelhardt
4513783a02 add tests 2025-10-14 15:48:16 +02:00
Emil J. Tywoniak
e9aedf505c chtype: replace publish pass with chtype -publish_icells 2025-10-14 15:01:48 +02:00
Miodrag Milanovic
d92cf2f5b0 Compile abc when submodule updates 2025-10-14 14:54:56 +02:00
Miodrag Milanovic
d3d3a9f1ea Update ABC 2025-10-14 14:47:17 +02:00
Emil J
109abd3224
Merge pull request #5421 from YosysHQ/emil/sort-pass 
sort: init
 2025-10-14 10:51:25 +02:00
github-actions[bot]
25f2a88770 Bump version 2025-10-14 00:22:29 +00:00
Emil J. Tywoniak
e5edd2acdb sort: init 2025-10-13 17:32:26 +02:00
Emil J
71eadc9ab5
Merge pull request #5418 from yrabbit/gw5-dff-and-memory 
Gowin. Reduce the range of flip-flop types.
 2025-10-13 17:26:56 +02:00
Emil J. Tywoniak
c46df9ffdc box_derive: rename -apply to -apply_derived_type 2025-10-13 17:24:32 +02:00
Emil J. Tywoniak
d7cea2c35c box_derive: add -apply 2025-10-13 17:24:32 +02:00
Emil J. Tywoniak
7d8f92e198 publish: add pass for renaming private cell types to public 2025-10-13 17:24:32 +02:00
Jannis Harder
84b5ec856e
Merge pull request #4320 from YosysHQ/ywb_asserts 
write_btor: Include `$assert` and `$assume` cells in -ywmap output
 2025-10-13 15:30:11 +02:00
Miodrag Milanovic
1f11b2c529 verific: Add src to message missed in #5406 2025-10-13 15:16:17 +02:00
Miodrag Milanovic
dc959cdf4a verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS 2025-10-13 15:16:17 +02:00