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16902 commits 133 branches 66 tags 59 MiB
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Author SHA1 Message Date
Robert O'Callahan
ab238c3145 Add ShardedHashSet 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan
87521df534 Add ShardedVector 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan
b079e5721c Add ParallelDispatchThreadPool 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan
898a288a99 Add work_pool_size, IntRange, item_range_for_worker, and ThreadIndex 
We'll use these later in this PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan
13d9fffdb9 Work around std::reverse miscompilation with empty range 
This causes problems when compiling with fuzzing instrumenation enabled.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan
bd7f2d9ba4 Make log_error() work in a Multithreaded context. 
`log_error()` causes an exit so we don't have to try too hard here. The main
thing is to ensure that we normally are able to exit without causing a stack
overflow due to recursive asserts about not being in a `Multithreaded` context.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan
7af5dbae35 Add IdString::unescape() method 
We've already talked about adding this as an alternative to `log_id()`, and we'll
need it later in this PR.
 2026-03-06 02:03:21 +00:00
abhinavputhran
6cd66aed47 setundef: rename process loop variable and respect selection in -init mode 2026-03-05 17:51:01 -05:00
abhinavputhran
df283fa1c9 setundef: use selected_processes() per review feedback 2026-03-05 11:22:00 -05:00
abhinavputhran
4e54853e35 setundef: use selected_processes() per review feedback 2026-03-05 11:16:07 -05:00
Justin Zaun
d9737acc31 gowin: remove lib_whitebox from latch sim cells 
Latches are sequential elements and don't need lib_whitebox.
 2026-03-05 16:04:23 +01:00
Justin Zaun
9288889e20 gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
 2026-03-05 16:04:23 +01:00
Miodrag Milanović
95d738edc0
Merge pull request #5726 from YosysHQ/emil/double-expose-yosys_celltypes 
celltypes: include newcelltypes to allow legacy code access to migrat…
 2026-03-05 11:36:36 +00:00
Emil J
629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Emil J. Tywoniak
23eb38fe3f celltypes: include newcelltypes to allow legacy code access to migrated yosys_celltypes 2026-03-05 11:59:20 +01:00
Lofty
da83c93673 analogdevices: fix SHIFTX name 2026-03-05 05:37:13 +00:00
Lofty
f3efa51b3e analogdevices: fix SHREG name 2026-03-05 05:37:13 +00:00
Lofty
e2e8245be9 analogdevices: fix MUXF78 name 2026-03-05 05:37:13 +00:00
Lofty
c747466a7a analogdevices: update missed T40LP timings 2026-03-05 05:37:13 +00:00
Lofty
91740645a9 analogdevices: update T40LP timings 2026-03-05 05:37:13 +00:00
Lofty
709746b184 analogdevices: update T16FFC timings 2026-03-05 05:37:13 +00:00
Lofty
cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Lofty
241db706e1 analogdevices: double LUT RAM cost 2026-03-05 05:37:13 +00:00
Lofty
3592d42d3b analogdevices: ignore $assert cells 2026-03-05 05:37:13 +00:00
Krystine Sherwin
5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Krystine Sherwin
f06018306d analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2026-03-05 05:37:13 +00:00
Krystine Sherwin
95ef0cd788 analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2026-03-05 05:37:13 +00:00
Lofty
8a09cc5463 analogdevices: LUT RAM only on positive edge 2026-03-05 05:37:13 +00:00
Lofty
dea8c275ff analogdevices: DSP tweaks 2026-03-05 05:37:12 +00:00
Lofty
39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Lofty
891b89f60d analogdevices: remove cells_xtra 2026-03-05 05:37:12 +00:00
Lofty
4954fc980f analogdevices: timings for t40lp 2026-03-05 05:37:12 +00:00
Lofty
2c3876671b analogdevices: use single tech param 2026-03-05 05:37:12 +00:00
Lofty
0a2b6a4f21 analogdevices: expreso does not care about clock buffers 2026-03-05 05:37:12 +00:00
Lofty
6ee0bfa913 analogdevices: prepare for t40lp timings 2026-03-05 05:37:12 +00:00
Krystine Sherwin
9dcffc3dbf analogdevices: Adding RBRAM2 and -tech 2026-03-05 05:37:12 +00:00
Krystine Sherwin
99e26d80b0 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-03-05 05:37:12 +00:00
Krystine Sherwin
9be3cfb3f9 analogdevices: Update lutram.ys test 2026-03-05 05:37:12 +00:00
Krystine Sherwin
376f746bc9 analogdevices: Native LUTRAM primitives 2026-03-05 05:37:12 +00:00
Lofty
30a03886a5 analogdevices: LUTRAM config 2026-03-05 05:37:12 +00:00
Lofty
ae5325fe53 analogdevices: update timing model 2026-03-05 05:37:12 +00:00
Lofty
c4bec4e8b8 I thought I removed this... 2026-03-05 05:37:12 +00:00
Lofty
85eb07d14d analogdevices: user retargeting 2026-03-05 05:37:12 +00:00
Lofty
c9f6d7b2d4 analogdevices: more housekeeping 2026-03-05 05:37:12 +00:00
Lofty
f659cbd159 analogdevices: remove some extra cells! 2026-03-05 05:37:12 +00:00
Lofty
6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Lofty
4f2f064262 synth_analogdevices: remove scopeinfo cells 2026-03-05 05:37:12 +00:00
Lofty
d5ea7f7016 Create synth_analogdevices 2026-03-05 05:37:12 +00:00
Lofty
4caffa7ebd
Merge pull request #5725 from yrabbit/disable-wm-2 
GOWIN. Disable read-before-write mode.
 2026-03-05 05:36:28 +00:00
Andrew Pullin
6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00