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Code Activity
15629 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
George Rennie
b788de9329 smtbmc: escape path identifiers 
* also changes the print format for cover statements to be more uniform
  with the asserts, allowing easier parsing of cover path
* this allows diambiguation of properties with the same name but
  different paths (see https://github.com/YosysHQ/sby/issues/296)
 2024-09-24 03:01:49 +01:00
Akash Levy
08fe6f66aa Fix functional 2024-09-23 06:56:12 -07:00
Akash Levy
a5c115f333 Update yosys-slang dep 2024-09-23 06:28:46 -07:00
Akash Levy
9193b0e324
Merge branch 'YosysHQ:main' into main 2024-09-23 06:27:58 -07:00
N. Engelhardt
8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail 2024-09-23 15:19:48 +02:00
Akash Levy
ed2c65314b Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
Akash Levy
9e9d4359d4 Smallfix 2024-09-23 05:57:09 -07:00
Akash Levy
6b9c45a841 Enable only the test suites we need 2024-09-23 05:39:56 -07:00
Akash Levy
db14842d9c Skip some various tests and fix scopeinfo to match our convention 2024-09-23 05:39:39 -07:00
Akash Levy
138228d96e Update Verific README 2024-09-23 05:35:48 -07:00
Akash Levy
fb32031273 Skip combo loop test and mark wreduce as failing (FIXME) 2024-09-23 05:35:27 -07:00
Akash Levy
79a14e2072 Skip opt_lut test 2024-09-23 05:35:03 -07:00
Akash Levy
a4bc124e3b Add abc back for testing 2024-09-23 05:30:40 -07:00
Akash Levy
0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy
0b8d951493 Add synopsys VHDL libs by default in GHDL 2024-09-23 04:05:27 -07:00
Akash Levy
2d771a352e Clean up Verific tests 2024-09-23 04:05:08 -07:00
Akash Levy
2c3d2b3ec6 Clocking works with -formal flag 2024-09-22 08:01:16 -07:00
Akash Levy
69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy
d655766c49 Smallfix 2024-09-22 06:57:28 -07:00
Akash Levy
89f9035a98 Fix VHDL checking 2024-09-22 06:45:47 -07:00
Akash Levy
7d5dac7255 More apt location for whereami 2024-09-22 06:02:20 -07:00
Akash Levy
f1ab51ce5b Clean up and remove hdl_file_sort 2024-09-22 05:58:17 -07:00
Akash Levy
facb9e8abe Disable plugins and slang for now 2024-09-22 05:24:23 -07:00
Akash Levy
f0b1d2cac5 Small changes 2024-09-22 01:11:26 -07:00
Akash Levy
3b8c607dfd Update yosys-slang 2024-09-21 22:18:50 -07:00
Akash Levy
7f38ea8721 Update yosys-slang 2024-09-19 16:43:01 -07:00
Akash Levy
494eba8d66 Update yosys-slang 2024-09-19 16:36:30 -07:00
Martin Povišer
9018d06a33 quicklogic: Avoid carry chains in division mapping 
The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.

For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
 2024-09-19 12:18:47 +02:00
Akash Levy
4cf9bb86ca Smallfix 2024-09-19 01:04:29 -07:00
Akash Levy
7988a61f8c Use enable debug and switch order of Verific opt passes 2024-09-19 00:48:31 -07:00
Akash Levy
03f740e2a4 Undo annoying commit bdc43c6592 2024-09-18 22:05:23 -07:00
Akash Levy
db0317afc5 Add support for int stuff 2024-09-18 16:46:53 -07:00
Akash Levy
1801bb966a Smallfix for slang support 2024-09-18 16:19:38 -07:00
Akash Levy
c71203d5f9 Fix slang install dir 2024-09-18 16:15:51 -07:00
Akash Levy
2d139c8735 Smallfix to remove top/bottom-bound attributes 2024-09-18 14:46:13 -07:00
Martin Povišer
f168b2f4b1 read_xaiger2: Update box handling 2024-09-18 16:55:02 +02:00
Martin Povišer
3a1b003cc3 celltypes: Fix $buf eval 2024-09-18 16:55:02 +02:00
Martin Povišer
5f8d7ff170 Start new write_xaiger2 backend for export w/ boxes 2024-09-18 16:55:02 +02:00
Martin Povišer
ea765686b6 aiger2: Adjust hierarchy/port handling 2024-09-18 16:55:02 +02:00
Martin Povišer
2a3e907da8 aiger2: Adjust typing 2024-09-18 16:42:56 +02:00
Martin Povišer
72d65063c3 aiger2: Ignore benign cells 2024-09-18 16:42:56 +02:00
Martin Povišer
1ab7f29933 Start read_xaiger2 -sc_mapping 2024-09-18 16:42:56 +02:00
Martin Povišer
6cecf19ff4 aiger2: Ingest $bmux 2024-09-18 16:42:56 +02:00
Martin Povišer
1cfb9023c4 aiger2: Use REDUCE for reduction ops 2024-09-18 16:42:56 +02:00
Martin Povišer
6c1fa45995 aiger2: Ingest $pmux 2024-09-18 16:42:56 +02:00
Martin Povišer
d5756eb9be tests: Add trivial liberty -unit_delay test 2024-09-18 16:17:03 +02:00
Martin Povišer
31476e89b6 tests: Avoid temporary script file 2024-09-18 16:17:03 +02:00
Martin Povišer
4976abb867 read_liberty: Optionally import unit delay arcs 2024-09-18 16:17:03 +02:00
Akash Levy
a7b71684cc Updates 2024-09-17 22:43:23 -07:00
Akash Levy
9bb6daa43a
Merge branch 'YosysHQ:main' into main 2024-09-17 22:42:22 -07:00