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Author	SHA1	Message	Date
Akash Levy	c71203d5f9	Fix slang install dir	2024-09-18 16:15:51 -07:00
Akash Levy	2d139c8735	Smallfix to remove top/bottom-bound attributes	2024-09-18 14:46:13 -07:00
Martin Povišer	f168b2f4b1	read_xaiger2: Update box handling	2024-09-18 16:55:02 +02:00
Martin Povišer	3a1b003cc3	celltypes: Fix $buf eval	2024-09-18 16:55:02 +02:00
Martin Povišer	5f8d7ff170	Start new write_xaiger2 backend for export w/ boxes	2024-09-18 16:55:02 +02:00
Martin Povišer	ea765686b6	aiger2: Adjust hierarchy/port handling	2024-09-18 16:55:02 +02:00
Martin Povišer	2a3e907da8	aiger2: Adjust typing	2024-09-18 16:42:56 +02:00
Martin Povišer	72d65063c3	aiger2: Ignore benign cells	2024-09-18 16:42:56 +02:00
Martin Povišer	1ab7f29933	Start read_xaiger2 -sc_mapping	2024-09-18 16:42:56 +02:00
Martin Povišer	6cecf19ff4	aiger2: Ingest $bmux	2024-09-18 16:42:56 +02:00
Martin Povišer	1cfb9023c4	aiger2: Use REDUCE for reduction ops	2024-09-18 16:42:56 +02:00
Martin Povišer	6c1fa45995	aiger2: Ingest $pmux	2024-09-18 16:42:56 +02:00
Martin Povišer	d5756eb9be	tests: Add trivial liberty -unit_delay test	2024-09-18 16:17:03 +02:00
Martin Povišer	31476e89b6	tests: Avoid temporary script file	2024-09-18 16:17:03 +02:00
Martin Povišer	4976abb867	read_liberty: Optionally import unit delay arcs	2024-09-18 16:17:03 +02:00
Akash Levy	a7b71684cc	Updates	2024-09-17 22:43:23 -07:00
Akash Levy	9bb6daa43a	Merge branch 'YosysHQ:main' into main	2024-09-17 22:42:22 -07:00
github-actions[bot]	4d581a97d6	Bump version	2024-09-18 00:19:41 +00:00
Akash Levy	9f44ec8aa1	Merge branch 'YosysHQ:main' into main	2024-09-17 15:24:05 -07:00
Martin Povišer	9db1ca83fc	aiger2: Drop empty_lit() as a function	2024-09-17 13:58:07 +02:00
Martin Povišer	dbc937b2a7	aiger2: Describe supported cells in help	2024-09-17 13:55:58 +02:00
Martin Povišer	e4b24e8200	aiger2: Fix literal typing	2024-09-17 13:55:58 +02:00
Martin Povišer	8e29675a23	aiger2: Support $bwmux, comparison operators	2024-09-17 13:55:58 +02:00
Martin Povišer	d7128cb787	aiger2: Use shorthands	2024-09-17 13:55:58 +02:00
Martin Povišer	e59387e5a9	aiger2: Add aigsize as a second user of index	2024-09-17 13:55:58 +02:00
Martin Povišer	de8a2fb936	aiger2: Fix duplicate symbols on multibit ports	2024-09-17 13:55:58 +02:00
Martin Povišer	5671c10173	aiger2: Add strashing option	2024-09-17 13:55:58 +02:00
Martin Povišer	fa39227416	aiger2: Support $pos	2024-09-17 13:55:58 +02:00
Martin Povišer	fb26945a20	Start an 'aiger2' backend	2024-09-17 13:55:58 +02:00
Martin Povišer	4cfdb7ab50	Adjust operation naming in aigmap test	2024-09-17 13:55:58 +02:00
Martin Povišer	a553b7c0c7	Merge pull request #3967 from YosysHQ/claire/bufnorm ... Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command	2024-09-17 11:27:23 +02:00
Martin Povišer	eeffca9470	simlib: Add $buf disclaimer	2024-09-17 10:46:20 +02:00
Martin Povišer	e13ace675e	dump: Update help after option removal	2024-09-17 10:46:20 +02:00
Martin Povišer	38de01807e	Mark bufnorm experimental	2024-09-17 10:46:20 +02:00
Martin Povišer	865df26fac	Adjust buf-normalized mode	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	80119386c0	Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	8bb70bac8d	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d027ead4b5	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	4d469f461b	Add coarse-grain $buf buffer cell type ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	f4b7ea5fb3	Improvements in "bufnorm" pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	32808a0393	Improvements and fixes to "bufnorm" cmd ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Claire Xenia Wolf	d0b5dfa6ef	Add bufnorm pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2024-09-17 10:46:20 +02:00
Akash Levy	e4f1f5a96c	Merge branch 'YosysHQ:main' into main	2024-09-16 19:14:49 -07:00
Akash Levy	44789c9f6c	Move ram opt around	2024-09-16 18:56:48 -07:00
github-actions[bot]	c8846243c2	Bump version	2024-09-17 00:16:41 +00:00
Akash Levy	76b072151d	Bump yosys-slang	2024-09-16 07:12:31 -07:00
Akash Levy	e4edea1b25	Update	2024-09-16 07:03:38 -07:00
Akash Levy	210ec6585f	Merge branch 'YosysHQ:main' into main	2024-09-16 06:59:25 -07:00
Emil J	f8ad371254	Merge pull request #4594 from yrabbit/cpu-wip ... Gowin. Add the EMCU primitive.	2024-09-16 15:41:14 +02:00
Emil J	52382c6544	Merge pull request #4583 from YosysHQ/emil/clock_gate ... clockgate: centralize clock enables out of FFs	2024-09-16 15:41:01 +02:00