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									 Clifford Wolf | b10f0088d1 | Added Yosys 0.5 Changelog | 2015-02-08 12:03:51 +01:00 |  | 
				
					
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									 Clifford Wolf | c3ce824af0 | Various updates to CodingReadme | 2015-02-08 12:03:51 +01:00 |  | 
				
					
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									 Clifford Wolf | 5170b86108 | Added equiv_add | 2015-02-08 11:59:38 +01:00 |  | 
				
					
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									 Clifford Wolf | 234a45a3d5 | Ignore explicit assignments to constants in HDL code | 2015-02-08 00:58:03 +01:00 |  | 
				
					
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									 Clifford Wolf | c8305e3a6d | Fixed a bug with autowire bit size (removed leftover from when we tried to auto-size the wires) | 2015-02-08 00:48:23 +01:00 |  | 
				
					
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									 Clifford Wolf | fbb16712f1 | fixed typo | 2015-02-08 00:16:59 +01:00 |  | 
				
					
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									 Clifford Wolf | bbfc1bd7cf | Added "yosys-config --build modname.so cppsources.." | 2015-02-08 00:14:07 +01:00 |  | 
				
					
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									 Clifford Wolf | 05d4223fb6 | Added SigSpec::has_const() | 2015-02-08 00:01:51 +01:00 |  | 
				
					
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									 Clifford Wolf | 0da320f151 | Cleanup in add_share_file make macro | 2015-02-08 00:01:31 +01:00 |  | 
				
					
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									 Clifford Wolf | 2ef812d67e | Removed "make mklibyosys" | 2015-02-07 19:05:06 +01:00 |  | 
				
					
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									 Clifford Wolf | 743da01e9e | Improved building of plugins | 2015-02-07 19:04:06 +01:00 |  | 
				
					
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									 Clifford Wolf | cc400b279a | Added "make uninstall" | 2015-02-07 17:46:46 +01:00 |  | 
				
					
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									 Clifford Wolf | dce1fae777 | Added cell->known(), cell->input(portname), cell->output(portname) | 2015-02-07 11:40:19 +01:00 |  | 
				
					
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									 Clifford Wolf | d5e30978e9 | Added "select -read" | 2015-02-06 10:01:22 +01:00 |  | 
				
					
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									 Clifford Wolf | ac7d5e0658 | Auto-detect TCL version | 2015-02-05 23:39:26 +01:00 |  | 
				
					
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									 Clifford Wolf | a038787c9b | Added onehot attribute | 2015-02-04 18:52:54 +01:00 |  | 
				
					
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									 Clifford Wolf | 8805c24640 | Fixed opt_clean performance bug | 2015-02-04 16:34:06 +01:00 |  | 
				
					
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									 Clifford Wolf | 853e949c0e | Disabled (unused) Xilinx tristate buffers | 2015-02-04 16:33:59 +01:00 |  | 
				
					
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									 Clifford Wolf | a8f4a099b5 | Using design->selected_modules() in opt_* | 2015-02-03 23:45:01 +01:00 |  | 
				
					
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									 Clifford Wolf | 5b41470e15 | Skip blackbox modules in design->selected_modules() | 2015-02-03 23:12:23 +01:00 |  | 
				
					
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									 Clifford Wolf | 8514fe79db | Added "yosys -L logfile" | 2015-02-03 23:12:23 +01:00 |  | 
				
					
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									 Clifford Wolf | 30ec64656b | Merge branch 'master' of github.com:cliffordwolf/yosys | 2015-02-01 23:07:00 +01:00 |  | 
				
					
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									 Clifford Wolf | bebbf2e5a4 | no support for 6-series xilinx devices | 2015-02-01 23:06:44 +01:00 |  | 
				
					
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									 Clifford Wolf | 6eb34038f4 | Merge pull request #48 from rubund/master Fixed typos found by lintian | 2015-02-01 22:55:52 +01:00 |  | 
				
					
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									 Clifford Wolf | 893fe87a33 | Improved performance in equiv_simple | 2015-02-01 22:50:48 +01:00 |  | 
				
					
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									 Ruben Undheim | 49649d6ef0 | Fixed typos found by lintian | 2015-02-01 21:49:55 +01:00 |  | 
				
					
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									 Clifford Wolf | 3cbfa3815e | Removed old XST-based xilinx examples | 2015-02-01 17:10:46 +01:00 |  | 
				
					
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									 Clifford Wolf | 816fe6bbe0 | Added Xilinx example for Basys3 board | 2015-02-01 17:09:34 +01:00 |  | 
				
					
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									 Clifford Wolf | 6978f3a77b | Added EDIF backend support for multi-bit cell ports | 2015-02-01 15:43:35 +01:00 |  | 
				
					
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									 Clifford Wolf | 1b159bc955 | Added missing ports and parameters to xilinx brams | 2015-02-01 15:42:59 +01:00 |  | 
				
					
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									 Clifford Wolf | 1df81f92ce | Added "make mklibyosys", some minor API changes | 2015-02-01 13:38:46 +01:00 |  | 
				
					
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									 Clifford Wolf | 3fe2441185 | Minor README changes | 2015-02-01 00:57:12 +01:00 |  | 
				
					
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									 Clifford Wolf | b59bb8a528 | Removed TODO list from README file | 2015-02-01 00:48:22 +01:00 |  | 
				
					
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									 Clifford Wolf | 9948ff2d8a | Added yosys_banner(), Updated Copyright range | 2015-02-01 00:39:59 +01:00 |  | 
				
					
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									 Clifford Wolf | 07326943e7 | Added <algorithm> include to hashlib.h | 2015-02-01 00:27:07 +01:00 |  | 
				
					
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									 Clifford Wolf | 9abbeefe6e | Using selections in "ls" command | 2015-02-01 00:13:19 +01:00 |  | 
				
					
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									 Clifford Wolf | fb8c755726 | Shorter "dump" options | 2015-01-31 23:52:36 +01:00 |  | 
				
					
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									 Clifford Wolf | 8dfa105255 | Bugfix in opt_const $eq -> buffer code | 2015-01-31 23:25:32 +01:00 |  | 
				
					
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									 Clifford Wolf | 67218443be | Log msg change | 2015-01-31 21:26:53 +01:00 |  | 
				
					
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									 Clifford Wolf | 1d92915a55 | Fixed equiv_make for partially undriven nets (e.g. after "clean -purge") | 2015-01-31 21:07:42 +01:00 |  | 
				
					
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									 Clifford Wolf | bc86b4a7e9 | Added "equiv_induct -undef" | 2015-01-31 13:58:04 +01:00 |  | 
				
					
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									 Clifford Wolf | e9cfc4a453 | Added "equiv_simple -undef" | 2015-01-31 13:06:41 +01:00 |  | 
				
					
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									 Clifford Wolf | f80f5b721d | Added "equiv_make -blacklist <file> -encfile <file>" | 2015-01-31 12:08:20 +01:00 |  | 
				
					
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									 Clifford Wolf | cb9d0a414d | Synced RTLIL::unescape_id() to log_id() behavior | 2015-01-30 22:51:16 +01:00 |  | 
				
					
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									 Clifford Wolf | bedd46338f | Added "fsm -encfile" | 2015-01-30 22:46:53 +01:00 |  | 
				
					
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									 Clifford Wolf | aabd5097ed | More log_id() stuff | 2015-01-30 22:22:52 +01:00 |  | 
				
					
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									 Clifford Wolf | 114a78d11a | Some cleanups in log.cc | 2015-01-30 22:12:26 +01:00 |  | 
				
					
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									 Clifford Wolf | 9ebf803cbe | Improved an error message | 2015-01-28 00:46:00 +01:00 |  | 
				
					
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									 Clifford Wolf | df64542288 | Fixed bug in equiv_miter | 2015-01-28 00:34:30 +01:00 |  | 
				
					
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									 Clifford Wolf | 23e54bda81 | Added "sat -show-ports" | 2015-01-27 23:04:28 +00:00 |  |