mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 13:29:12 +00:00 
			
		
		
		
	Bugfix in opt_const $eq -> buffer code
This commit is contained in:
		
							parent
							
								
									67218443be
								
							
						
					
					
						commit
						8dfa105255
					
				
					 1 changed files with 4 additions and 4 deletions
				
			
		| 
						 | 
				
			
			@ -524,11 +524,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 | 
			
		|||
			RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
 | 
			
		||||
			RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
 | 
			
		||||
 | 
			
		||||
			if (a.is_fully_const()) {
 | 
			
		||||
			if (a.is_fully_const() && !b.is_fully_const()) {
 | 
			
		||||
				cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type.str());
 | 
			
		||||
				RTLIL::SigSpec tmp = cell->getPort("\\A");
 | 
			
		||||
				cell->setPort("\\A", cell->getPort("\\B"));
 | 
			
		||||
				cell->setPort("\\B", tmp);
 | 
			
		||||
				cell->setPort("\\A", b);
 | 
			
		||||
				cell->setPort("\\B", a);
 | 
			
		||||
				std::swap(a, b);
 | 
			
		||||
			}
 | 
			
		||||
 | 
			
		||||
			if (b.is_fully_const()) {
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue