Emil J. Tywoniak
8e17fb0266
consteval: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a0f87dc2d1
modtools: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a9463d1aee
newcelltypes: fix non-cells
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
e3f9911e33
newcelltypes: refactor
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
07ec8708e4
share: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
3212dfaf1f
newcelltypes: fix unit test
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
2d7d6ca10b
newcelltypes: unit test
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
7e9e88c2ec
newcelltypes: bounds check
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
9e59f05c25
newcelltypes: wrap design celltypes support
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
35ccaa60d7
newcelltypes: TurboCellTypes -> StaticCellTypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
6adc08b0e5
opt_expr: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
3671d577a0
opt_clean: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a61455645d
newcelltypes: init
2026-03-04 12:22:14 +01:00
Miodrag Milanovic
cf4d4ff23d
CI: add support for merge queue
2026-03-04 11:35:16 +01:00
Miodrag Milanović
05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix
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abc9: preserve topological-loop asserts with targeted SCC fallback
2026-03-04 11:09:38 +01:00
Miodrag Milanović
d3e297fcd4
Merge pull request #5722 from YosysHQ/release/v0.63
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Yosys Release v0.63
2026-03-04 09:31:22 +01:00
Miodrag Milanovic
228052bfb3
Next dev cycle
2026-03-04 08:45:13 +01:00
Miodrag Milanovic
70a11c6bf0
Release version 0.63
2026-03-04 07:46:57 +01:00
Miodrag Milanovic
b7d013e6bf
Fix help message for equiv passes
2026-03-04 07:46:40 +01:00
Emil J. Tywoniak
126492742b
read_liberty: fix for msvc
2026-03-03 17:34:58 +01:00
Emil J
04113eb95d
Merge pull request #5714 from likeamahoney/auto-proc-vars
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support automatic lifetime qualifier on procedural variables
2026-03-03 17:31:37 +01:00
Emil J. Tywoniak
5b4603c54f
dfflibmap: fix formal $dffsr tests with sat, prove "no s&r" assumption only needed when appropriate
2026-03-03 10:35:03 +01:00
Emil J. Tywoniak
22916aaab1
read_liberty: model clear_preset_variable correctly
2026-03-03 10:35:03 +01:00
Emil J. Tywoniak
024408004a
dfflibmap: allow formal dffsr mapping tests with clk2fflogic
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
6f74c54c02
async2sync: $dffsr has undef output on S&R
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
857bc02710
liberty: warn if dffsr has clear&preset well defined
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
2dddc53ccf
dfflibmap: test dffsr and dffsre from proc with equiv
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
c13a623dbc
dfflibmap: test dffsr with either priority liberty file
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
ffb76a3486
dfflibmap: test dffsr mapping without assume
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
a53104379d
clk2fflogic: $dffsr has undef output on S&R
2026-03-03 10:34:29 +01:00
KrystalDelusion
1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc
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Update help text for rename -witness and write_aiger -ywmap
2026-03-02 09:29:25 +13:00
likeamahoney
e9442194f2
support automatic lifetime qualifier on procedural variables
2026-02-27 20:42:52 +03:00
Miodrag Milanović
687a36af38
Merge pull request #5711 from YosysHQ/gowin_warning
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gowin: remove spurious warning
2026-02-27 14:04:27 +01:00
Miodrag Milanovic
7f1f247c56
gowin: remove spurious warning
2026-02-27 13:12:32 +01:00
Miodrag Milanović
2dd71c3ba2
Merge pull request #5709 from YosysHQ/update_abc
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Update ABC as per 2026-02-27
2026-02-27 08:32:34 +01:00
Miodrag Milanovic
b3caec1a93
Update ABC as per 2026-02-27
2026-02-27 07:55:34 +01:00
Andrew Pullin
5970be33fb
abc9: preserve topological-loop asserts with targeted SCC fallback
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A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.
Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).
To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.
Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
2026-02-26 22:30:32 -08:00
nella
2c52546e2a
Fix docs.
2026-02-25 16:42:05 +01:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
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equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Miodrag Milanović
fd1ac58767
Merge pull request #5706 from YosysHQ/remove-flake-lock
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Remove already disabled CI job
2026-02-25 11:15:33 +01:00
Miodrag Milanovic
31f7d0d92d
Remove already disabled CI job
2026-02-25 10:36:46 +01:00
Miodrag Milanović
53d8eb43ff
Merge pull request #5702 from YosysHQ/verific_build_all
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Check verific configurations
2026-02-23 09:41:59 +01:00
Miodrag Milanovic
b51110a50b
Build various Verific configurations
2026-02-23 09:01:55 +01:00
Krystine Sherwin
fd311c5501
tests/arch/gowin: Add wr_en test
2026-02-22 09:00:37 +01:00
Krystine Sherwin
2386923b8f
gowin: Fix bram ADA byte enables
2026-02-22 09:00:37 +01:00
Miodrag Milanović
fb653c4181
Merge pull request #5700 from YosysHQ/wasi_speedup
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CI: WASI - Applying YoWASP changes to script
2026-02-20 18:00:24 +01:00
Miodrag Milanovic
68e47ebcfe
CI: WASI - Applying YoWASP changes to script
2026-02-20 15:23:45 +01:00
Miodrag Milanović
0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify
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abc9: verify post-mapping equivalence by default
2026-02-20 13:41:11 +01:00
Krystine Sherwin
094481739f
memory_libmap: Add -force-params
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Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2026-02-20 10:57:00 +00:00
Emil J
13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks
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aigerparse: add some bounds checks
2026-02-20 11:53:49 +01:00
