Merge pull request #5722 from YosysHQ/release/v0.63

Yosys Release v0.63

CHANGELOG

@@ -2,9 +2,24 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.62 .. Yosys 0.63-dev
+Yosys 0.63 .. Yosys 0.64-dev
 --------------------------
 
+Yosys 0.62 .. Yosys 0.63
+--------------------------
+ * Various
+    - Added DSP inference for Gowin GW1N and GW2A.
+    - Added support for subtract in preadder for Xilinx arch.
+    - Added infrastructure to run a sat solver as a command.
+
+ * New commands and options
+    - Added "-ignore-unknown-cells" option to "equiv_induct"
+      and "equiv_simple" pass.
+    - Added "-force-params" option to "memory_libmap" pass.
+    - Added "-select-solver" option to "sat" pass.
+    - Added "-default_params" option to "write_verilog" pass.
+    - Added "-nodsp" option to "synth_gowin" pass.
+
 Yosys 0.61 .. Yosys 0.62
 --------------------------
  * Various

Makefile

@@ -161,7 +161,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.62
+YOSYS_VER := 0.63
 
 ifneq (, $(shell command -v git 2>/dev/null))
 ifneq (, $(shell git rev-parse --git-dir 2>/dev/null))

docs/source/conf.py

@@ -6,7 +6,7 @@ import os
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2026 YosysHQ GmbH'
-yosys_ver = "0.62"
+yosys_ver = "0.63"
 
 # select HTML theme
 html_theme = 'furo-ys'

passes/equiv/equiv_induct.cc

@@ -174,7 +174,7 @@ struct EquivInductPass : public Pass {
 		log("Only selected $equiv cells are proven and only selected cells are used to\n");
 		log("perform the proof.\n");
 		log("\n");
-		EquivBasicConfig::help("4");
+		log("%s", EquivBasicConfig::help("4"));
 		log("\n");
 		log("This command is very effective in proving complex sequential circuits, when\n");
 		log("the internal state of the circuit quickly propagates to $equiv cells.\n");

passes/equiv/equiv_simple.cc

@@ -428,7 +428,7 @@ struct EquivSimplePass : public Pass {
 		log("\n");
 		log("This command tries to prove $equiv cells using a simple direct SAT approach.\n");
 		log("\n");
-		EquivSimpleConfig::help("1");
+		log("%s", EquivSimpleConfig::help("1"));
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, Design *design) override