Add comments in setup-build-env/action.yml for where to document prereqs (and the separation between build/run and test).
Add some initial (very basic) text for `test_suites.rst`, listing prereqs and how to run the tests (with subsections for the different optional tests, which is currently docs, functional and unit).
Add sphinx-inline-tabs, use it for tidying up prereq instructions based on OS/platform (mostly helpful in the test suites doc where there are multiple sections split by OS).
Also fixes some single backticks that should be double backtick.
For these primitives, Gowin decided to use a different option for
describing ports—directly in the module header, i.e.
``` verilog
module ADC(input CLK);
```
instead of
``` verilog
module ADC(CLK);
input CLK;
```
Since this one-time parser becomes too confusing, it is easier to simply
add ADC descriptions as they are from a separate file, especially since
these primitives are only available in the GW5A series.
Test:
``` shell
yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a"
```
The old version of Yosys simply won't compile the design due to the lack
of port descriptions, while the new version will compile without errors.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Process the WRITE_MODE in the GW5A series in a more concise manner.
You can check it in the same way as in
https://github.com/YosysHQ/yosys/pull/5440
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.
Here, we prohibit the generation of BSRAM with this mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules.
This addresses https://github.com/YosysHQ/yosys/issues/2545, allowing Yosys to be better packaged in non-FHS environments such as Nix.
