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Code Activity
15841 commits 124 branches 59 tags 44 MiB
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25 commits

Author SHA1 Message Date
Emil J. Tywoniak
7f030c986c tests: report time per target, eliminate interleaving lines on stdout 2025-09-19 18:31:27 +02:00
Robert O'Callahan
8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Charlotte
d130f7fca2 tests: use /usr/bin/env for bash. 2023-08-12 11:59:39 +10:00
Marcin Kościelnicki
7e0e42f907 xilinx: Add simulation model for DSP48 (Virtex 4). 2020-01-29 01:40:00 +01:00
Marcin Kościelnicki
dadaf7ed78 xilinx: Test our DSP48A/DSP48A1 simulation models. 2019-12-23 20:36:43 +01:00
Eddie Hung
e992dbf2c5 Add pattern detection support for DSP48E1 model, check against vendor 2019-09-18 10:45:04 -07:00
David Shah
b8cd4ad64a DSP48E1 sim model: add SIMD tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:39:35 +01:00
David Shah
57aeb4cc01 DSP48E1 model: test CE inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:32:43 +01:00
David Shah
d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah
e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah
f6605c7dc0 DSP48E1 sim model: Comb, no pre-adder, mode working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:26:44 +01:00
David Shah
f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00
David Shah
ccfb4ff2a9 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 09:31:34 +01:00
Clifford Wolf
3481f46d1e Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
Clifford Wolf
8520b7fbe0 Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
Clifford Wolf
d19866615b Added Xilinx test case for initialized brams 2015-04-06 13:27:11 +02:00
Clifford Wolf
d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Clifford Wolf
8d295730e5 Refactoring of memory_bram and xilinx brams 2015-01-18 19:05:29 +01:00
Clifford Wolf
584c5f3937 Cleanups in xilinx bram descriptions 2015-01-07 01:28:18 +01:00
Clifford Wolf
08c13f635c Xilinx RAMB36/RAMB18 memory_bram support complete 2015-01-06 23:54:33 +01:00
Clifford Wolf
ec2eef89fa Towards Xilinx bram support 2015-01-06 23:21:52 +01:00
Clifford Wolf
9474928672 Towards Xilinx bram support 2015-01-06 15:26:33 +01:00
Clifford Wolf
081e1a49f8 Towards Xilinx bram support 2015-01-06 14:26:51 +01:00
Clifford Wolf
9c7f47bbd5 Towards Xilinx bram support 2015-01-06 13:33:51 +01:00
Clifford Wolf
9ea2511fe8 Towards Xilinx bram support 2015-01-05 13:59:04 +01:00