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https://github.com/YosysHQ/yosys
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tests: report time per target, eliminate interleaving lines on stdout
This commit is contained in:
parent
d5053033e4
commit
7f030c986c
13 changed files with 14 additions and 19 deletions
2
Makefile
2
Makefile
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@ -954,7 +954,7 @@ makefile-tests: $(MK_TEST_DIRS:%=makefile-tests/%)
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+cd $(dir $*) && bash run-test.sh
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# this one spawns submake on each
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makefile-tests/%: %/run-test.mk $(TARGETS) $(EXTRA_TARGETS)
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$(MAKE) -C $* -f run-test.mk
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stdbuf -oL -eL $(MAKE) -C $* -f run-test.mk
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+@echo "...passed tests in $*"
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test: makefile-tests abcopt-tests seed-tests
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@ -43,7 +43,7 @@ for dbits in $dbits_list; do
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{
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echo "bram1_$id/ok:"
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echo " @cd bram1_$id && bash run.sh"
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echo " @echo -n '[$id]'"
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echo " @echo '[$id]'"
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echo " @touch \$@"
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} >> bram1.mk
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all_list="$all_list bram1_$id/ok"
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@ -10,12 +10,12 @@ for arch in ../../techlibs/*; do
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arch_name=$(basename -- $arch)
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if [ "${defines[$arch_name]}" ]; then
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for def in ${defines[$arch_name]}; do
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echo -n "Test $path -D$def ->"
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echo "Test $path -D$def ->"
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iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path
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echo " ok"
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done
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else
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echo -n "Test $path ->"
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echo "Test $path ->"
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iverilog -t null -I$arch -g2005-sv $path
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echo " ok"
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fi
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@ -23,7 +23,7 @@ for arch in ../../techlibs/*; do
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done
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for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
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echo -n "Test $path ->"
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echo "Test $path ->"
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iverilog -t null $path
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echo " ok"
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done
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@ -29,10 +29,9 @@ python3 generate.py -c $count $seed
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for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
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idx=$( printf "%05d" $i )
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echo "temp/uut_${idx}.log: temp/uut_${idx}.ys temp/uut_${idx}.v"
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echo " @echo -n '[$i]'"
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echo " @../../yosys -ql temp/uut_${idx}.out temp/uut_${idx}.ys"
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echo " @mv temp/uut_${idx}.out temp/uut_${idx}.log"
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echo " @grep -q 'SAT proof finished' temp/uut_${idx}.log && echo -n K || echo -n T"
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echo " @grep -q 'SAT proof finished' temp/uut_${idx}.log && echo K || echo T"
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all_targets="$all_targets temp/uut_${idx}.log"
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done
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echo "$all_targets"
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@ -9,8 +9,7 @@ generate_target() {
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echo "all: $target_name"
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echo ".PHONY: $target_name"
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echo "$target_name:"
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printf "\t@%s\n" "$test_command"
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printf "\t@echo 'Passed %s'\n" "$target_name"
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printf "\t@/usr/bin/env time -f \"PASS $target_name %%e seconds\" $test_command >/dev/null 2>/dev/null\n"
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}
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# $ generate_ys_test ys_file [yosys_args]
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@ -17,7 +17,7 @@ shift "$((OPTIND-1))"
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${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v
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for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
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echo -n "Testing expectations for $f .."
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echo "Testing expectations for $f .."
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../../yosys -f verilog -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
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if grep -q expect-wr-ports $f; then
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grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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@ -32,7 +32,6 @@ python3 generate.py -c $count $seed
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echo "all: test-$idx"
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echo "test-$idx:"
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printf "\t@%s\n" \
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"echo -n [$i]" \
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"../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys"
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done
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} > temp/makefile
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@ -21,7 +21,6 @@ python3 generate.py -c $count $seed
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cd temp
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echo "running tests.."
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for ((i = 0; i < $count; i++)); do
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echo -n "[$i]"
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idx=$( printf "%05d" $i )
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../../../yosys -qq uut_${idx}.ys
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iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v
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@ -24,7 +24,6 @@ python3 generate.py -c $count $seed
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echo "running tests.."
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for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
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echo -n "[$i]"
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idx=$( printf "%05d" $i )
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../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys
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done
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@ -7,7 +7,7 @@ if [ $# != 1 ]; then
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exit 1
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fi
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echo -n "Test: $1 ->"
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echo "Test: $1 ->"
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../../yosys $1.ys >$1.log_stdout 2>$1.log_stderr || {
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echo "ERROR!"
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exit 1
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@ -9,7 +9,7 @@ STDERRFILE=${TESTNAME}.log_stderr
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echo "" > $STDOUTFILE
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echo "" > $STDERRFILE
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echo -n "Test: ${TESTNAME} -> "
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echo "Test: ${TESTNAME} -> "
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set -e
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@ -129,7 +129,7 @@ do
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status_prefix="Test: $bn "
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else
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status_prefix=""
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echo -n "Test: $bn "
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echo "Test: $bn "
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fi
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if [ "$ext" == sv ]; then
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@ -3,7 +3,7 @@
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set -e
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echo -n " TOP first - "
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echo " TOP first - "
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../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
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read_verilog << EOV
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module TOP(a, y);
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@ -22,7 +22,7 @@ echo -n " TOP first - "
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hierarchy -auto-top
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EOY
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echo -n " TOP last - "
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echo " TOP last - "
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../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
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read_verilog << EOV
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module aoi12(a, y);
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@ -41,7 +41,7 @@ echo -n " TOP last - "
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hierarchy -auto-top
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EOY
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echo -n " no explicit top - "
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echo " no explicit top - "
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../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
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read_verilog << EOV
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module aoi12(a, y);
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