3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-09 09:21:58 +00:00

tests: report time per target, eliminate interleaving lines on stdout

This commit is contained in:
Emil J. Tywoniak 2025-09-19 18:09:47 +02:00
parent d5053033e4
commit 7f030c986c
13 changed files with 14 additions and 19 deletions

View file

@ -954,7 +954,7 @@ makefile-tests: $(MK_TEST_DIRS:%=makefile-tests/%)
+cd $(dir $*) && bash run-test.sh
# this one spawns submake on each
makefile-tests/%: %/run-test.mk $(TARGETS) $(EXTRA_TARGETS)
$(MAKE) -C $* -f run-test.mk
stdbuf -oL -eL $(MAKE) -C $* -f run-test.mk
+@echo "...passed tests in $*"
test: makefile-tests abcopt-tests seed-tests

View file

@ -43,7 +43,7 @@ for dbits in $dbits_list; do
{
echo "bram1_$id/ok:"
echo " @cd bram1_$id && bash run.sh"
echo " @echo -n '[$id]'"
echo " @echo '[$id]'"
echo " @touch \$@"
} >> bram1.mk
all_list="$all_list bram1_$id/ok"

View file

@ -10,12 +10,12 @@ for arch in ../../techlibs/*; do
arch_name=$(basename -- $arch)
if [ "${defines[$arch_name]}" ]; then
for def in ${defines[$arch_name]}; do
echo -n "Test $path -D$def ->"
echo "Test $path -D$def ->"
iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path
echo " ok"
done
else
echo -n "Test $path ->"
echo "Test $path ->"
iverilog -t null -I$arch -g2005-sv $path
echo " ok"
fi
@ -23,7 +23,7 @@ for arch in ../../techlibs/*; do
done
for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
echo -n "Test $path ->"
echo "Test $path ->"
iverilog -t null $path
echo " ok"
done

View file

@ -29,10 +29,9 @@ python3 generate.py -c $count $seed
for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
idx=$( printf "%05d" $i )
echo "temp/uut_${idx}.log: temp/uut_${idx}.ys temp/uut_${idx}.v"
echo " @echo -n '[$i]'"
echo " @../../yosys -ql temp/uut_${idx}.out temp/uut_${idx}.ys"
echo " @mv temp/uut_${idx}.out temp/uut_${idx}.log"
echo " @grep -q 'SAT proof finished' temp/uut_${idx}.log && echo -n K || echo -n T"
echo " @grep -q 'SAT proof finished' temp/uut_${idx}.log && echo K || echo T"
all_targets="$all_targets temp/uut_${idx}.log"
done
echo "$all_targets"

View file

@ -9,8 +9,7 @@ generate_target() {
echo "all: $target_name"
echo ".PHONY: $target_name"
echo "$target_name:"
printf "\t@%s\n" "$test_command"
printf "\t@echo 'Passed %s'\n" "$target_name"
printf "\t@/usr/bin/env time -f \"PASS $target_name %%e seconds\" $test_command >/dev/null 2>/dev/null\n"
}
# $ generate_ys_test ys_file [yosys_args]

View file

@ -17,7 +17,7 @@ shift "$((OPTIND-1))"
${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v
for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
echo -n "Testing expectations for $f .."
echo "Testing expectations for $f .."
../../yosys -f verilog -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
if grep -q expect-wr-ports $f; then
grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||

View file

@ -32,7 +32,6 @@ python3 generate.py -c $count $seed
echo "all: test-$idx"
echo "test-$idx:"
printf "\t@%s\n" \
"echo -n [$i]" \
"../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys"
done
} > temp/makefile

View file

@ -21,7 +21,6 @@ python3 generate.py -c $count $seed
cd temp
echo "running tests.."
for ((i = 0; i < $count; i++)); do
echo -n "[$i]"
idx=$( printf "%05d" $i )
../../../yosys -qq uut_${idx}.ys
iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v

View file

@ -24,7 +24,6 @@ python3 generate.py -c $count $seed
echo "running tests.."
for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
echo -n "[$i]"
idx=$( printf "%05d" $i )
../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys
done

View file

@ -7,7 +7,7 @@ if [ $# != 1 ]; then
exit 1
fi
echo -n "Test: $1 ->"
echo "Test: $1 ->"
../../yosys $1.ys >$1.log_stdout 2>$1.log_stderr || {
echo "ERROR!"
exit 1

View file

@ -9,7 +9,7 @@ STDERRFILE=${TESTNAME}.log_stderr
echo "" > $STDOUTFILE
echo "" > $STDERRFILE
echo -n "Test: ${TESTNAME} -> "
echo "Test: ${TESTNAME} -> "
set -e

View file

@ -129,7 +129,7 @@ do
status_prefix="Test: $bn "
else
status_prefix=""
echo -n "Test: $bn "
echo "Test: $bn "
fi
if [ "$ext" == sv ]; then

View file

@ -3,7 +3,7 @@
set -e
echo -n " TOP first - "
echo " TOP first - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module TOP(a, y);
@ -22,7 +22,7 @@ echo -n " TOP first - "
hierarchy -auto-top
EOY
echo -n " TOP last - "
echo " TOP last - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module aoi12(a, y);
@ -41,7 +41,7 @@ echo -n " TOP last - "
hierarchy -auto-top
EOY
echo -n " no explicit top - "
echo " no explicit top - "
../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
read_verilog << EOV
module aoi12(a, y);