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Code Activity
9859 commits 121 branches 59 tags 72 MiB
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475 commits

Author SHA1 Message Date
SergeyDegtyar
757c476f62 Add smoke tests to tests/xilinx 2019-10-17 17:10:02 +02:00
SergeyDegtyar
2ae7dec530 Add tests for Xilinx UG901 examples 2019-10-17 17:08:38 +02:00
Clifford Wolf
e84cedfae4 Use "(id)" instead of "id" for types as temporary hack 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-14 05:24:31 +02:00
Miodrag Milanovic
ef417fb1b3 Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix 2019-10-04 12:20:49 +02:00
Miodrag Milanovic
b932654964 Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic 2019-10-04 10:52:16 +02:00
Clifford Wolf
17cb916cc8 Update ABC to git rev 623b5e8 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 14:05:21 +02:00
Clifford Wolf
be8efd7c7b Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 12:26:08 +02:00
David Shah
abc155715d sv: Add test scripts for typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
Sergey
e092c4ae6b
Merge branch 'master' into SergeyDegtyar/efinix 2019-10-01 11:04:32 +03:00
Sergey
d99b1e3261
Merge branch 'master' into SergeyDegtyar/anlogic 2019-10-01 10:57:09 +03:00
Eddie Hung
0bbd1b6364 Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys into eddie/pr1352 2019-09-30 14:57:55 -07:00
whitequark
5c5881695d
Merge pull request #1406 from whitequark/connect_rpc 
rpc: new frontend
 2019-09-30 17:38:20 +00:00
whitequark
99a7f39084 rpc: new frontend. 
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
 2019-09-30 15:53:11 +00:00
whitequark
8f2bdff7b9 libs: import json11. 
This commit imports the code from upstream commit
dropbox/json11@8ccf1f0c5e.
 2019-09-30 15:53:11 +00:00
Clifford Wolf
7ed13297b1 Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-30 17:08:38 +02:00
SergeyDegtyar
1070f2e90b Add new tests for Efinix architecture. 
Problems/questions:
	- fsm.ys. equiv_opt -assert failed because of unproven cells;
	- latches.ys,tribuf.ys - internal cells present;
	- memory.ys - sat called with -verify and proof did fail.
 2019-09-23 15:51:41 +03:00
SergeyDegtyar
27377c4663 Add new tests for Anlogic architecture 
Problems/questions:
	- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
		Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
	- Internal cell type $_TBUF_  is present.
 2019-09-23 12:12:02 +03:00
Clifford Wolf
36df37a734 Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-16 13:05:41 +02:00
Clifford Wolf
486cbddd26 Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-10 18:42:45 +02:00
Clifford Wolf
58ec1df4c2 Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 19:05:13 +02:00
Emily
a9af28694c Use $(shell :; ...) in Makefile to force shell 
Did you think that `$(shell command -v ...)` would actually get run by
the shell? Foolish mortal; GNU Make is obviously far more wise than
thee, as it optimizes it to a direct -- and hence broken (since
`command` is a shell builtin) -- exec. This horrifying contortion
ensures that an actual shell runs the command and fixes the behaviour.

@Shizmob found the source of this misbehaviour; turns out gmake has a
hard-coded, incomplete list of shell builtins:

    715c787dc6/src/job.c (L2691)

This contains `command`, but the whole function is full of horrible
heuristic garbage so who knows. I'm so sorry.
 2019-09-05 00:43:30 +01:00
Emily
a7ea6a6fcf Replace which with command -v in Makefile too 2019-09-04 19:01:00 +01:00
SergeyDegtyar
11f330ed22 Add tests for ECP5 architecture 2019-09-03 11:53:37 +03:00
Sergey
5dda8f39a6
Merge pull request #2 from YosysHQ/master 
Pull from upstream
 2019-08-29 21:09:40 +03:00
Clifford Wolf
89695fd3ab Bump YOSYS_VER 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-29 12:05:26 +02:00
Eddie Hung
32eef26ee2 Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40 2019-08-28 12:18:32 -07:00
SergeyDegtyar
fe58790f37 Revert "Add tests for ecp5" 
This reverts commit 2270ead09f.
 2019-08-28 09:49:58 +03:00
SergeyDegtyar
2270ead09f Add tests for ecp5 2019-08-28 09:47:03 +03:00
SergeyDegtyar
980830f7b8 Revert "Add tests for ecp5 architecture." 
This reverts commit 134d3fea90.
 2019-08-27 18:28:05 +03:00
SergeyDegtyar
134d3fea90 Add tests for ecp5 architecture. 2019-08-27 18:12:18 +03:00
Clifford Wolf
fdbcf78909 Add "make bumpversion" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-27 10:15:25 +02:00
Clifford Wolf
8a4c6e6563 Merge tag 'yosys-0.9' 2019-08-26 11:14:22 +02:00
Clifford Wolf
1979e0b1f2 Yosys 0.9 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-26 10:37:53 +02:00
Miodrag Milanovic
7fafaa896d do not require boost if pyosys is not used 2019-08-22 11:57:46 -07:00
Miodrag Milanovic
e5dac8096d do not require boost if pyosys is not used 2019-08-22 20:43:52 +02:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen 2019-08-20 11:39:23 +02:00
SergeyDegtyar
153ec0541c Add new tests for ice40 architecture 2019-08-20 07:50:05 +03:00
whitequark
4a942ba7b9 proc_clean: fix order of switch insertion. 
Fixes #1268.
 2019-08-19 16:44:23 +00:00
Clifford Wolf
1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00
Eddie Hung
e34f2de55d Merge remote-tracking branch 'origin/master' into clifford/testfast 2019-08-18 21:29:15 -07:00
Clifford Wolf
9e940f1276 Speed up "make test" and related cleanups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:37:07 +02:00
Eddie Hung
51d28645da Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share 2019-08-16 13:40:29 -07:00
Clifford Wolf
73bf453929 Improvements in pmgen for recursive patterns 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 18:35:56 +02:00
Eddie Hung
13b7d2252e 'make clean' to not remove anything abc 2019-08-07 11:10:18 -07:00
Bogdan Vukobratovic
6a796accc0 Support various binary operators in opt_share 2019-08-04 19:06:38 +02:00
Miodrag Milanovic
2ec5a3ec92 Fix linking issue for new mxe and pthread 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
ce0de937f4 Fix yosys linking for mxe 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
e9c5f1b346 Fix formatting for msys2 mingw build using GetSize 2019-08-02 16:55:14 +02:00
Miodrag Milanovic
7a65ed19a5 Fix linking issue for new mxe and pthread 2019-08-01 17:30:02 +02:00
Miodrag Milanovic
3f633690ae Fix yosys linking for mxe 2019-08-01 17:28:07 +02:00