mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-30 13:19:05 +00:00
Code Activity
15879 commits 121 branches 58 tags 57 MiB
Commit graph

2008 commits

Author SHA1 Message Date
Emil J. Tywoniak
d31bfdd66a reduce OS ifdefs, refactor getting dirs and filenames from paths to files 2025-09-23 17:29:02 +02:00
Robert O'Callahan
1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Emil J
a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
Jannis Harder
79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
 2025-09-17 14:01:09 +02:00
Robert O'Callahan
a1141f1a4c Remove some unnecessary .c_str() calls to the result of unescape_id() 2025-09-16 23:12:14 +00:00
Robert O'Callahan
d276529d46 Remove .c_str() calls from parameters to log_file_info() 2025-09-16 23:06:28 +00:00
Robert O'Callahan
548deba259 Remove .c_str() calls from parameters to log_file_warning() 2025-09-16 23:03:45 +00:00
Robert O'Callahan
a7c46f7b4a Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
Robert O'Callahan
d1fd6de6da Remove .c_str() calls from parameters to log_header() 2025-09-16 23:00:42 +00:00
Robert O'Callahan
5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Emil J. Tywoniak
73747f6928 read_verilog: add -relativeshare for synthesis reproducibility testing 2025-09-16 15:47:35 +02:00
Robert O'Callahan
1a367b907c Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
Robert O'Callahan
f65ca488ec Update frontends to avoid bits() 2025-09-16 03:17:23 +00:00
Xing Guo
3d2bb1db17 verilog_parser: replace manual AST node allocation with typed midrule actions 
Use Bison's typed midrule actions to construct AST_FCALL nodes
with std::unique_ptr, replacing manual 'new' and extra->ast_stack
management. This improves type safety, ensures proper ownership, and
eliminates potential memory leaks.

Ref: https://www.gnu.org/software/bison/manual/html_node/Typed-Midrule-Actions.html
 2025-09-13 11:23:42 +08:00
Jannis Harder
193b057983
Merge pull request #5341 from rocallahan/more-varargs-conversion 
More varargs conversion
 2025-09-12 18:09:42 +02:00
Jannis Harder
dd9627ed05
Merge pull request #5336 from rocallahan/remove-log-cstr 
Remove `.c_str()` calls from `log()`/`log_error()`
 2025-09-12 14:09:48 +02:00
Robert O'Callahan
f4699e2b10 Remove unnecessary c_str() calls from err_at_loc/warn_at_loc 2025-09-12 06:21:56 +00:00
Robert O'Callahan
8cd3c069d6 Use C++ stringf machinery in verilog_error 2025-09-12 06:21:56 +00:00
Robert O'Callahan
733b6f0124 Remove unnecessary usage of .c_str() in parameters to input_error() 2025-09-12 06:03:05 +00:00
Robert O'Callahan
ad4ef8b775 Make AstNode::input_error use C++ stringf machinery 2025-09-12 06:01:32 +00:00
Robert O'Callahan
e0ae7b7af4 Remove .c_str() calls from log()/log_error() 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
 2025-09-11 20:59:37 +00:00
Xing Guo
9a6f25fb73 verilog_parser: Use unique_ptr<> to store the attribute list. 
We can get rid of the new / delete statements and free_attr() and we
don't need to manage the memory manually.
 2025-09-11 09:57:45 +08:00
Emil J
5278b9cfe1
Merge pull request #5332 from YosysHQ/parse_specify-rebased 
Add state_dependent_path_declaration so that `ifnone` can be parsed (rebased)
 2025-09-09 21:53:04 +02:00
Robert O'Callahan
9764fa5c41 Remove superfluous/wasteful .c_str()s in log_file_warning() filename parameter 2025-09-09 15:41:03 +02:00
Michael Kupfer
75316e8c49 Add state_dependent_path_declaration so that ifnone can be parsed 2025-09-09 13:04:52 +02:00
Jannis Harder
c468ee7add
Merge pull request #5304 from rocallahan/idstring-stringf 
Support `IdString` parameters in `stringf()` and remove `.c_str()` in a lot of places
 2025-09-08 20:29:20 +02:00
Xing Guo
c30fd46ea3 Fix handling of cases that look like sva labels again. 
Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels.  After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:

```
➜  /tmp yosys -p 'read -sv a1.v'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)

-- Running command `read -sv a1.v' --

1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜  /tmp cat a1.v
module test(input wire A);
  localparam TEST = 1;
  always_comb begin
    case (A)
      TEST: assert(1);
    endcase
  end
endmodule
```

We encountered this issue before but with a different error message[^1],

[^1]: https://github.com/YosysHQ/yosys/issues/862
 2025-09-05 11:54:13 +08:00
Robert O'Callahan
c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Ethan Mahintorabi
d10190606c verilog: Lower required bison version to 3.6 
We're currently on version 3.6 of bison at Google, and Yosys
still correctly builds with it. This should better reflect
the actual requirements rather than an overly restrictive
check. If features from 3.8 are required it seems like bumping
would be appropriate.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2025-08-21 08:26:33 +01:00
Ethan Mahintorabi
7f0130efce verilog: Fix missing sstream include 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2025-08-21 08:26:20 +01:00
Emil J
dbb977aa8b
Merge pull request #5288 from YosysHQ/emil/demote-verilog-parser-errors-again 
verilog: demote some parser errors to warnings again
 2025-08-13 12:52:50 +02:00
Emil J. Tywoniak
1603828b30 verilog_parser: fix locations of warnings for restrict keyword 2025-08-13 10:56:48 +02:00
Emil J. Tywoniak
910ff3ff36 verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
Emil J. Tywoniak
8582136a45 simplify: fix $initstate segfault 2025-08-12 12:39:36 +02:00
Emil J. Tywoniak
642e041f77 const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
99ab73424d verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
5195f81257 ast: fix import node 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
df8422d244 verilog_lexer: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
740ed3fc1c ast: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
646c45e6b8 ast: remove null_check as dead code 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
25d2a8ce3a simplify: simplify 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
97bc0088d8 simplify: std::gcd 2025-08-11 13:34:10 +02:00
Krystine Sherwin
d3e33a3be5 simplify.cc: Drop unused debug prints 
At least the ones added by this PR.  There are some unused debug prints that are *changed* by this PR, but I've left them.
 2025-08-11 13:34:10 +02:00
Krystine Sherwin
9b882c32c1 frontends/ast: More usage of auto 
For consistency.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
5b62616b63 preproc: formatting 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
9a10f4c02f verilog_lexer, verilog_parser: remove comment 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
ae65b4fc84 verilog_lexer: fix fallthrough warning 2025-08-11 13:34:10 +02:00
Emil J
39c5c256c0 verilog_lexer: remove comment 
Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
abb8b8d28b preproc: formatting 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
85b5a7d08b verilog: fix build dependency graph 2025-08-11 13:34:10 +02:00