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Author	SHA1	Message	Date
Eddie Hung	e5aa3feb1b	Merge remote-tracking branch 'origin/master' into xc7mux	2019-06-18 12:19:22 -07:00
Eddie Hung	4ca847a217	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-18 11:49:54 -07:00
Eddie Hung	8e0a47fb92	Really permute Xilinx LUT mappings as default LUT6.I5:A6	2019-06-18 11:48:48 -07:00
Eddie Hung	8f5e6d73ff	Revert "Fix (do not) permute LUT inputs, but permute mux selects" ... This reverts commit da3d2eedd2.	2019-06-18 11:35:21 -07:00
Eddie Hung	3d283e69f8	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-18 09:51:28 -07:00
Eddie Hung	b304744d15	Clean up	2019-06-18 09:50:37 -07:00
Eddie Hung	da3d2eedd2	Fix (do not) permute LUT inputs, but permute mux selects	2019-06-18 09:49:57 -07:00
Clifford Wolf	64947453e2	Merge pull request #1086 from udif/pr_elab_sys_tasks2 ... Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)	2019-06-18 16:52:08 +02:00
Eddie Hung	2b0e28b261	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 22:29:34 -07:00
Eddie Hung	608a95eb01	Fix copy-pasta issue	2019-06-17 22:29:22 -07:00
Eddie Hung	59b4e69d16	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 22:25:14 -07:00
Eddie Hung	2a35c4ef94	Permute INIT for +/xilinx/lut_map.v	2019-06-17 22:24:35 -07:00
Eddie Hung	75f8b4cf10	Simplify comment	2019-06-17 19:14:41 -07:00
Eddie Hung	9d56c0d525	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 18:25:35 -07:00
Eddie Hung	840562943f	Update LUT7/8 delays to take account for [ABC]OUTMUX delay	2019-06-17 17:06:01 -07:00
Eddie Hung	8d40830ee4	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 13:33:47 -07:00
Eddie Hung	4d6d593fe3	&scorr before &sweep, remove &retime as recommended	2019-06-17 13:32:08 -07:00
Eddie Hung	4b9eefe3b6	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 13:20:29 -07:00
Eddie Hung	63fc879a5f	Copy not move parameters/attributes	2019-06-17 13:19:45 -07:00
Eddie Hung	0c9cf89239	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 12:59:05 -07:00
Eddie Hung	b45d06d7a3	Fix leak removing cells during ABC integration; also preserve attr	2019-06-17 12:54:24 -07:00
Eddie Hung	76a72283e2	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 10:38:54 -07:00
Eddie Hung	c15ee827f4	Try -W 300	2019-06-17 10:29:06 -07:00
Eddie Hung	7250c57c5a	Re-enable &dc2	2019-06-17 10:28:51 -07:00
Clifford Wolf	c23bbc4291	Add timescale and generated-by header to yosys-smtbmc MkVcd ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-16 23:12:03 +02:00
Eddie Hung	1ec450d6bf	Try -W 300	2019-06-16 12:08:03 -07:00
Eddie Hung	5f9ba3ea41	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-16 12:05:07 -07:00
Eddie Hung	fb90d8c18c	Cleanup	2019-06-16 09:34:26 -07:00
Eddie Hung	842c110357	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-15 05:48:47 -07:00
Eddie Hung	bf312043d4	Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O	2019-06-15 05:45:16 -07:00
Eddie Hung	627ea0b2a9	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-14 14:20:36 -07:00
Eddie Hung	7ff8330d1e	Leave breadcrumb behind	2019-06-14 13:34:40 -07:00
Eddie Hung	46e69ee934	Remove redundant condition	2019-06-14 13:31:18 -07:00
Eddie Hung	9b55e69755	Revert "Cleanup/optimise toposort in write_xaiger" ... This reverts commit 1948e7c846. Restores old toposort with optimisations	2019-06-14 13:29:36 -07:00
Eddie Hung	4d7516f459	Revert "Cleanup/optimise toposort in write_xaiger" ... This reverts commit 1948e7c846. Restores old toposort with optimisations	2019-06-14 13:28:47 -07:00
Eddie Hung	6c5ed8b660	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-14 13:15:12 -07:00
Eddie Hung	746f70a9ce	Update comment	2019-06-14 13:10:46 -07:00
Eddie Hung	0fa6a441f1	Check that whiteboxes are synthesisable	2019-06-14 13:08:38 -07:00
Eddie Hung	2d85725604	Get rid of compiler warnings	2019-06-14 13:07:56 -07:00
Eddie Hung	13e2e8df11	Update CHANGELOG	2019-06-14 12:50:30 -07:00
Eddie Hung	b63b2a0bd4	Revert "Remove wide mux inference" ... This reverts commit 738fdfe8f5.	2019-06-14 12:50:24 -07:00
Eddie Hung	691e145cda	Merge branch 'xaig' into xc7mux	2019-06-14 12:46:52 -07:00
Eddie Hung	8fa74287a7	As per @daveshah1 remove async DFF timing from xilinx	2019-06-14 12:43:20 -07:00
Eddie Hung	7876b5b8be	Cover __APPLE__ too for little to big endian	2019-06-14 12:40:51 -07:00
Eddie Hung	a632799d5b	Update abc9 -D doc	2019-06-14 12:29:46 -07:00
Eddie Hung	e391fc8e7b	Enable "abc9 -D <num>" for timing-driven synthesis	2019-06-14 12:28:01 -07:00
Eddie Hung	a48b5bfaa5	Further cleanup based on @daveshah1	2019-06-14 12:25:06 -07:00
Eddie Hung	97d2656375	Resolve comments from @daveshah1	2019-06-14 12:00:02 -07:00
Eddie Hung	2e34859a6b	Add XC7_WIRE_DELAY macro to synth_xilinx.cc	2019-06-14 11:38:22 -07:00
Eddie Hung	ba4b4a0088	Update delays based on SymbiFlow/prjxray-db	2019-06-14 11:33:10 -07:00