2147 commits

Author	SHA1	Message	Date
Emil J. Tywoniak	e41ea6788e	genrtlil: intern action src as verbatim Twine ... add(std::string) tags bare strings as public names, so a single-source concat (which returns the lone ref unchanged) decoded with a spurious '\' prefix, splitting one source file into two in linecoverage output. add(Twine{}) stores the location string verbatim like set_src_attr. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>	2026-07-20 15:01:30 +02:00
Emil J. Tywoniak	3d2e268154	kernel: add SwitchRule signal_src ... (cherry picked from commit 53585db9f7)	2026-07-20 15:01:30 +02:00
Emil J. Tywoniak	c74bc43cfd	proc_mux, genrtlil: make use of case_src for better case condition vs block tracking ... (cherry picked from commit a24c260998)	2026-07-20 15:01:30 +02:00
Emil J. Tywoniak	0aaf46c692	verific: use SyncActions ... (cherry picked from commit f4a69805ae)	2026-07-20 15:01:30 +02:00
Emil J. Tywoniak	6f3b384ac4	rtlil: add source tracking to CaseRule actions ... (cherry picked from commit c36370f227)	2026-07-20 15:01:30 +02:00
Emil J. Tywoniak	9ac4905aeb	verilog: fix case location ... (cherry picked from commit 7713b5a811)	2026-07-20 15:01:30 +02:00
Emil J. Tywoniak	dad4961221	rtlil: replace SigSig actions with new type SyncAction ... (cherry picked from commit 94a53e08bc)	2026-07-20 15:01:30 +02:00
Emil J. Tywoniak	a6eeb7c1f4	WIP migration to twine	2026-07-20 13:57:10 +02:00
Emil J. Tywoniak	1976b526d6	aiger2: fix twines	2026-07-20 13:57:10 +02:00
Emil J. Tywoniak	0302a692c2	liberty: better twines	2026-07-20 13:57:10 +02:00
Emil J. Tywoniak	746324d576	aigerparse: better twines	2026-07-20 13:57:10 +02:00
Emil J. Tywoniak	628501c786	ast, flatten, hierarchy: canonically split hierarchical references into twines	2026-07-20 13:57:10 +02:00
Emil J. Tywoniak	92b16718c9	twine: fix replayability, reduce TwineSearch usage	2026-07-20 13:57:10 +02:00
Emil J. Tywoniak	f02025d2f1	rtlil_frontend: fix twine ordering	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	4799869e5b	rtlil_frontend: allocate meta block	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	c3ffd67a5a	WIP migration to twine	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	c08fb7f3ed	WIP migration to twine	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	65f35a88eb	WIP migration to twine	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	6a05403060	WIP migration to twine	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	0f884b6cba	twine: avoid TwinePool::lookup	2026-07-20 12:27:18 +02:00
Emil J. Tywoniak	7ce989d5f9	rtlil_frontend, rtlil_backend: dump statics as strings, comments for src	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	a5248849d9	WIP	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	b01a3694f0	WIP	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	77ad54139e	WIP	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	e952044215	WIP	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	7422b71802	WIP	2026-07-20 12:27:17 +02:00
Emil J. Tywoniak	1210d8e117	WIP	2026-07-20 12:27:02 +02:00
Emil J. Tywoniak	30bc1c23ee	WIP	2026-07-20 12:27:02 +02:00
Emil J. Tywoniak	10436f31cd	WIP	2026-07-20 12:27:02 +02:00
Emil J. Tywoniak	f508244f36	rtlil: fix masquerade	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	a1d13b821e	rtlil: set Module::design before name at all construction sites	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	be4d67d1a3	rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	3d87269697	rtlil: set Module* on inner-process AttrObjects at construction	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	d7f88dd3a0	rtlil: evacuate src_id_ from AttrObject to per-Design meta vector	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	0bff07d55c	rtlil: add Module* back-pointer to RTLIL::Memory	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	f017bb8a93	twine	2026-07-20 12:26:39 +02:00
Emil J. Tywoniak	cd9b1191f2	signorm: disable in passes that use swap_names	2026-07-17 23:32:34 +02:00
Miodrag Milanovic	30ba4328e7	Use system libs when available	2026-07-13 15:26:00 +02:00
Michael Baier	8f0028652a	long long to int truncation checks	2026-07-10 14:36:39 +02:00
Michael Baier	eb4e29810e	Fixed Overflow error in checking width	2026-07-09 14:34:56 +02:00
Michael Baier	42092cbc77	Adding width checks to frontend	2026-07-09 14:34:56 +02:00
Lofty	75286287c6	Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 ... Move rename logic to abc_ops_reintegrate	2026-07-09 08:46:46 +00:00
Martin Povišer	ff8a867764	Bump sv-elab to 2026-07-07	2026-07-07 15:20:19 +02:00
Miodrag Milanovic	05c0adae77	Slang frontend integration	2026-07-06 15:49:56 +02:00
Miodrag Milanovic	a689342207	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
Miodrag Milanovic	48a3dcc02a	End of file fix	2026-06-23 07:23:41 +02:00
Lofty	091d2a7814	Move rename logic to abc_ops_reintegrate	2026-06-19 10:46:47 +01:00
nella	5d7486115a	Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 ... Fix: `read_verilog` doesn't respect `signed` keyword	2026-06-18 16:53:37 +00:00
Krystine Sherwin	b79c7c008d	simplify.cc: Fix crash when identifier matches module ... Also update one of the AST debug prints that is guarded by an `#if 0` but was out of date.	2026-06-12 11:54:53 +12:00
Lofty	73c217133b	Merge pull request #5934 from YosysHQ/lofty/abc9-refactor-5 ... read_aiger: import standard-cell mappings from ABC	2026-06-08 09:38:34 +00:00