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Code Activity
yosys/frontends
History
Emil J. Tywoniak f508244f36 rtlil: fix masquerade
2026-07-20 12:26:39 +02:00
..
aiger rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
aiger2 read_aiger: import standard-cell mappings from ABC 2026-06-05 11:02:58 +01:00
ast rtlil: fix masquerade 2026-07-20 12:26:39 +02:00
blif rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
json rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
liberty rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
rpc rtlil: fix masquerade 2026-07-20 12:26:39 +02:00
rtlil rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
slang Use system libs when available 2026-07-13 15:26:00 +02:00
verific rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
verilog End of file fix 2026-06-23 07:23:41 +02:00
CMakeLists.txt Use system libs when available 2026-07-13 15:26:00 +02:00