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Author SHA1 Message Date
Eddie Hung e31e21766d Try a different approach with 'muxcover' 2019-04-26 16:09:54 -07:00
Eddie Hung 76b7c5d4cc Merge remote-tracking branch 'origin/master' into xc7mux 2019-04-26 15:35:55 -07:00
Eddie Hung ea0e0722bb Where did this check come from!?! 2019-04-26 15:35:34 -07:00
Eddie Hung 6b9ca7cd6d Remove split_shiftx call 2019-04-26 15:32:58 -07:00
Eddie Hung dcc8a13e48 Revert "Merge branch 'eddie/split_shiftx' into xc7mux" 
This reverts commit 3042d58330, reversing
changes made to feff976454.
 2019-04-26 15:32:02 -07:00
Eddie Hung 8469d9fe9f Missing newline 2019-04-26 14:51:37 -07:00
Eddie Hung 4473fd1502 Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:14:33 -07:00
Eddie Hung 976d8030dc Actually use pm.st.shiftxB 2019-04-25 19:59:33 -07:00
Eddie Hung f14d7f0df6 Cleanup superseded 2019-04-25 19:43:41 -07:00
Eddie Hung 019c48b508 bitblast_shiftx -> split_shiftx 2019-04-25 19:38:35 -07:00
Eddie Hung fb4348f840 Fix for when B_WIDTH has trailing zeroes 2019-04-25 19:38:19 -07:00
Eddie Hung 880652283c Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux 2019-04-25 18:52:20 -07:00
Eddie Hung ece2c49e92 In order to indicate a failed pattern, blacklist? 2019-04-25 18:39:13 -07:00
Eddie Hung 0eb7150a57 Add test 2019-04-25 18:08:05 -07:00
Eddie Hung af3c374a35 Elaborate on help message 2019-04-25 17:35:39 -07:00
Eddie Hung 3042d58330 Merge branch 'eddie/split_shiftx' into xc7mux 2019-04-25 17:31:27 -07:00
Eddie Hung ccd0729456 Add split_shiftx command 2019-04-25 17:23:59 -07:00
Eddie Hung 8d00b9ef7e Make pmgen support files more generic 2019-04-25 17:23:46 -07:00
Eddie Hung feff976454 synth_xilinx to call bitblast_shiftx 2019-04-25 17:11:18 -07:00
Eddie Hung 408161ea3a
Misspelling 2019-04-25 16:46:13 -07:00
Eddie Hung eec314e262 Remove topo sort no-loop assertion, with test 2019-04-24 21:06:53 -07:00
Eddie Hung f96d82a5f1 Add -nocarry option to synth_xilinx 2019-04-24 16:46:41 -07:00
Eddie Hung bfd71e0990 Fix abc9 with (* keep *) wires 2019-04-23 16:11:14 -07:00
Eddie Hung 9d122d3c51 Refactor into AigerReader::post_process() 2019-04-23 15:06:19 -07:00
Clifford Wolf b2020ab44f
Merge pull request #957 from YosysHQ/oai4fix 
Fixes for OAI4 cell implementation
 2019-04-23 19:59:39 +02:00
David Shah 742c2f245d Fixes for OAI4 cell implementation 
Fixes #955 and the underlying issue in #954

Signed-off-by: David Shah <dave@ds0.me>
 2019-04-23 17:54:00 +01:00
Eddie Hung c6156f3118
Format some names using inline code 2019-04-23 09:01:10 -07:00
Eddie Hung f66792c43a
Fix spelling 2019-04-23 08:58:34 -07:00
Clifford Wolf c84cdc711c Remove some left-over log_dump() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 17:55:41 +02:00
Eddie Hung 60026842b2 Tweak 2019-04-22 17:59:56 -07:00
Eddie Hung 26e461f47d Fix for A_WIDTH == 2 but B_WIDTH==3 2019-04-22 17:58:28 -07:00
Eddie Hung 1fa2c36fbd Trim A_WIDTH by Y_WIDTH-1 2019-04-22 17:14:11 -07:00
Eddie Hung 69863f7698 Add comment 2019-04-22 16:58:44 -07:00
Eddie Hung 61161faefc Fix for mux_case_* mappings 2019-04-22 16:56:18 -07:00
Eddie Hung ac1e13819e Fix for non-pow2 width muxes 2019-04-22 14:26:13 -07:00
Eddie Hung d9daf09cf3
Merge pull request #914 from YosysHQ/xc7srl 
synth_xilinx to now infer SRL16E/SRLC32E
 2019-04-22 13:31:30 -07:00
Eddie Hung 75b96b1aff Add synth_xilinx -nomux option 2019-04-22 12:36:15 -07:00
Eddie Hung 79fb291dbe Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
Eddie Hung 4cfef7897f Merge branch 'xaig' into xc7mux 2019-04-22 11:58:59 -07:00
Eddie Hung eaf3c24772 Temporarily remove 'r' extension 2019-04-22 11:54:19 -07:00
Eddie Hung 4486a98fd5 Merge remote-tracking branch 'origin/xc7srl' into xc7mux 2019-04-22 11:45:49 -07:00
Eddie Hung ec88129a5c Update help message 2019-04-22 11:38:23 -07:00
Eddie Hung b780c0a7de Allow POs to be PIs in XAIG 2019-04-22 11:22:29 -07:00
Eddie Hung 2c6358ea25 Remove kernel/cost.cc since master has refactored it 2019-04-22 11:21:17 -07:00
Eddie Hung 4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Clifford Wolf bc98a463a4
Merge pull request #952 from YosysHQ/clifford/fix370 
Determine correct signedness and expression width in for-loop unrolling
 2019-04-22 20:10:46 +02:00
Clifford Wolf 8ed4a53d99
Merge pull request #951 from YosysHQ/clifford/logdebug 
Add log_debug() framework
 2019-04-22 20:09:51 +02:00
Clifford Wolf 1d538ff1ec
Merge pull request #949 from YosysHQ/clifford/pmux2shimprove 
Add full_pmux feature to pmux2shiftx
 2019-04-22 20:01:43 +02:00
Clifford Wolf 3be5aac52c
Merge pull request #953 from YosysHQ/clifford/fix948 
Add support for zero-width signals to Verilog back-end
 2019-04-22 20:01:09 +02:00
Eddie Hung 0e76718720 Move 'shregmap -tech xilinx' into map_cells 2019-04-22 10:45:39 -07:00