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Code Activity
2797 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
df5ebfa0a0 Improved ice40_ffinit error reporting 2016-06-30 09:58:13 +02:00
Clifford Wolf
7cddab0788 Merge pull request #181 from rubund/input_logic_allowed 
Allow defining input ports as "input logic" in SystemVerilog
 2016-06-21 08:44:20 +02:00
Ruben Undheim
545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog 2016-06-20 20:16:37 +02:00
Clifford Wolf
541083cf32 Bugfix in "abc -script" handling 2016-06-19 22:19:19 +02:00
Clifford Wolf
9bca8ccd40 Merge branch 'sv_packages' of https://github.com/rubund/yosys 2016-06-19 15:48:40 +02:00
Clifford Wolf
ca91bccb6b Added "deminout" 2016-06-19 13:08:16 +02:00
Ruben Undheim
a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Clifford Wolf
9e28290b0f Added "read_blif -sop" 2016-06-18 12:33:13 +02:00
Clifford Wolf
5ffad4e073 Added $sop support to BLIF back-end 2016-06-18 12:28:49 +02:00
Ruben Undheim
178ff3e7f6 Added support for SystemVerilog packages with localparam definitions 2016-06-18 10:53:55 +02:00
Clifford Wolf
3380281e15 Added "dc2" to default ABC scripts 2016-06-17 20:15:35 +02:00
Clifford Wolf
7a4ee5da74 Fixed init issue in mem2reg_test2 test case 2016-06-17 20:15:11 +02:00
Clifford Wolf
f498204ae4 Added "abc -I <num> -P <num>" 2016-06-17 19:39:35 +02:00
Clifford Wolf
ebece2b8d5 Added $sop SAT model 2016-06-17 17:47:30 +02:00
Clifford Wolf
95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf
c3365034e9 Updated ABC to hg rev b5df6e2b76f0 2016-06-17 11:16:31 +02:00
Clifford Wolf
99edf24966 Added "nlutmap -assert" 2016-06-09 11:47:41 +02:00
Clifford Wolf
52b0b4e31e Do not run "wreduce" in "prep -ifx" 2016-06-08 12:14:32 +02:00
Clifford Wolf
2032e6d8e4 Added "proc_mux -ifx" 2016-06-06 17:15:50 +02:00
Clifford Wolf
dcf576641b Added "setundef -init" 2016-06-03 11:38:31 +02:00
Clifford Wolf
d2695e2bfa Fix all undef-muxes in dlatch input cone 2016-06-02 14:37:07 +02:00
Clifford Wolf
adfc80727c Avoid creating undef-muxes when inferring latches in proc_dlatch 2016-06-01 13:25:06 +02:00
Clifford Wolf
11f7b8a2a1 Added opt_expr support for div/mod by power-of-two 2016-05-29 12:17:36 +02:00
Clifford Wolf
766032c5f8 Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} 2016-05-27 17:55:03 +02:00
Clifford Wolf
ee071586c5 Fixed access-after-delete bug in mem2reg code 2016-05-27 17:25:33 +02:00
Clifford Wolf
e9ceec26ff fixed typos in error messages 2016-05-27 16:37:36 +02:00
Clifford Wolf
611f121cb9 Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop 2016-05-27 16:33:13 +02:00
Clifford Wolf
33742f4e8f Merge pull request #172 from zeldin/deterministic_hierarchy 
Made the expansion order of hierarchy deterministic
 2016-05-22 18:15:08 +02:00
Marcus Comstedt
e22e4d59b8 Made the expansion order of hierarchy deterministic 2016-05-22 16:41:26 +02:00
Clifford Wolf
8e9e793126 Some fixes in tests/asicworld/*_tb.v 2016-05-20 17:13:11 +02:00
Clifford Wolf
1e227caf72 Improvements and fixes in autotest.sh script and test_autotb 2016-05-20 16:58:02 +02:00
Clifford Wolf
884ec96787 Merge branch 'master' of https://github.com/Kmanfi/yosys 2016-05-20 16:48:50 +02:00
Clifford Wolf
f3983a0940 Also escape "=" in spice output 2016-05-20 16:43:13 +02:00
Clifford Wolf
060bf4819a Small improvements in Verilog front-end docs 2016-05-20 16:21:35 +02:00
Kaj Tuomi
8c3bc2ac0d Close opened dump file. 2016-05-19 11:53:29 +03:00
Kaj Tuomi
f6221ade95 Fix for Modelsim transcript line warp issue #164 2016-05-19 11:34:38 +03:00
Clifford Wolf
ffcdc53a18 Don't sign-extend memory bram initialization data 2016-05-15 00:05:30 +02:00
Clifford Wolf
864eeadcd9 Added missing "#define HASHLIB_H" 2016-05-14 11:43:20 +02:00
Clifford Wolf
d05115ceda Minor presentation fixes 2016-05-14 11:35:39 +02:00
Clifford Wolf
407cdea0bc Updated min GCC requirement to GCC 4.8 2016-05-11 09:31:53 +02:00
Clifford Wolf
b8b39472bb Added manual download link to README 2016-05-09 12:43:49 +02:00
Clifford Wolf
570014800a Include <cmath> in yosys.h 2016-05-08 10:50:39 +02:00
Clifford Wolf
fa76d51941 Merge pull request #162 from azonenberg/master 
Added GP_DELAY cell. Fixed several errors in simulation models.
 2016-05-08 10:22:01 +02:00
Andrew Zonenberg
47eace0b9f Added GP_DELAY cell 2016-05-07 21:29:26 -07:00
Andrew Zonenberg
41bbad4e4c Fixed typo in port name 2016-05-07 21:14:42 -07:00
Andrew Zonenberg
b5171541cd Fixed extra semicolon 2016-05-07 21:14:18 -07:00
Andrew Zonenberg
85ee88b0ee Fixed typo in parameter name 2016-05-07 21:14:00 -07:00
Andrew Zonenberg
a0c19aae55 Added simulation timescale declaration 2016-05-07 21:13:47 -07:00
Clifford Wolf
f103bfb9ba Fixes for MXE build 2016-05-07 10:53:18 +02:00