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Code Activity
12491 commits 122 branches 59 tags 72 MiB
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1730 commits

Author SHA1 Message Date
Eddie Hung
bb4164481d Do not ignore newline after AND in binary AIG 2019-02-11 11:51:44 -08:00
Eddie Hung
8886fa5506 addDff -> addDffGate as per @daveshah1 2019-02-08 13:17:53 -08:00
Eddie Hung
afc3c4b613 Fix tabulation 2019-02-08 13:17:02 -08:00
Eddie Hung
aa66d8f12f -module_name arg to go before -clk_name 2019-02-08 12:49:55 -08:00
Eddie Hung
391ec75b07 Add missing "[options]" to read_blif help 2019-02-08 12:41:39 -08:00
Eddie Hung
fb8ad440a3 Allow module name to be determined by argument too 2019-02-08 12:40:43 -08:00
Eddie Hung
f1befe1b44 Refactor into AigerReader class 2019-02-08 12:04:26 -08:00
Eddie Hung
2a8cc36578 Parse binary AIG files 2019-02-08 11:45:16 -08:00
Eddie Hung
09d758f0a3 Refactor to parse_aiger_header() 2019-02-08 10:54:31 -08:00
Eddie Hung
36c56bf412 Add comment 2019-02-08 08:37:44 -08:00
Eddie Hung
5e24251a61 Handle reset logic in latches 2019-02-08 08:37:18 -08:00
Eddie Hung
652e414392 Change literal vars from int to unsigned 2019-02-08 08:09:30 -08:00
Eddie Hung
fafa972238 Create clk outside of latch loop 2019-02-08 08:08:49 -08:00
Eddie Hung
02f603ac1a Handle latch symbols too 2019-02-08 08:05:27 -08:00
Eddie Hung
5a593ff41c Remove return after log_error 2019-02-08 08:04:48 -08:00
Eddie Hung
6dbeda1807 Add support for symbol tables 2019-02-08 08:03:40 -08:00
Eddie Hung
791f93181d Stub for binary AIGER 2019-02-08 07:31:04 -08:00
Eddie Hung
40db2f2eb6 Refactor 2019-02-06 14:58:47 -08:00
Eddie Hung
cc0b723484 WIP 2019-02-06 12:19:48 -08:00
Clifford Wolf
17ceab92a9 Bugfix in Verilog string handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 12:10:24 +01:00
Clifford Wolf
6d1e7e9403 Remove -m32 Verific eval lib build instructions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-04 15:03:49 +01:00
Clifford Wolf
1eb101a38a Improve VerificImporter support for writes to asymmetric memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:33:43 +01:00
Clifford Wolf
50b09de033 Fix VerificImporter asymmetric memories error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:05:23 +01:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Clifford Wolf
6dad191377 Add "read_ilang -[no]overwrite" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-23 15:45:09 +01:00
Clifford Wolf
fdf7c42181 Fix segfault in AST simplify 
(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 17:49:38 +01:00
Clifford Wolf
3d671630e2 Improve src tagging (using names and attrs) of cells and wires in verific front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 16:01:22 +01:00
whitequark
4effb38e6d read_ilang: allow slicing sigspecs. 2018-12-16 17:53:26 +00:00
Sylvain Munaut
58fb2ac818 verilog_parser: Properly handle recursion when processing attributes 
Fixes #737

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-12-14 12:48:00 +01:00
Clifford Wolf
910d94b212 Verific updates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:21:50 +01:00
Sylvain Munaut
86ce43999e Make return value of $clog2 signed 
As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-24 18:49:23 +01:00
Clifford Wolf
5387ccb041 Set Verific flag vhdl_support_variable_slice=1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 21:03:23 +01:00
Clifford Wolf
719e29404a Allow square brackets in liberty identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-05 12:33:33 +01:00
Clifford Wolf
36ea98385f Add warning for SV "restrict" without "property" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 15:57:17 +01:00
Clifford Wolf
64e0582c29 Various indenting fixes in AST front-end (mostly space vs tab issues) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 10:19:32 +01:00
ZipCPU
39f891aebc Make and dependent upon LSB only 2018-11-03 13:39:32 -04:00
Clifford Wolf
d86ea6badd Do not generate "reg assigned in a continuous assignment" warnings for "rand reg" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-01 15:25:24 +01:00
Clifford Wolf
5ab58d4930 Fix minor typo in error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-25 13:20:00 +02:00
Clifford Wolf
6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error 
More meaningful SystemVerilog/Verilog parser error messages
 2018-10-25 13:18:59 +02:00
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00
Clifford Wolf
23b69ca32b Improve read_verilog range out of bounds warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-20 23:48:53 +02:00
Ruben Undheim
436e3c0a7c Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim
d9a4381012 Fixed memory leak 2018-10-20 11:57:39 +02:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
Clifford Wolf
93d99559ef
Merge pull request #664 from tklam/ignore-verilog-protect 
Ignore protect endprotect
 2018-10-18 10:52:07 +02:00
Clifford Wolf
6ca493b88c Minor code cleanups in liberty front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-17 12:23:36 +02:00
Clifford Wolf
8395c18cb5
Merge pull request #660 from tklam/parse-liberty-detect-ff-latch 
Handling ff/latch in liberty files
 2018-10-17 12:21:17 +02:00
Clifford Wolf
38dbb44fa0
Merge pull request #638 from udif/pr_reg_wire_error 
Fix issue #630
 2018-10-17 12:13:18 +02:00
argama
097da32e1a ignore protect endprotect 2018-10-16 21:33:37 +08:00