Mohamed Gaber
9fa27dae3c
hotfix: fix new log functions being incompatible with pyosys
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Modify python wrapper generator script with corner-case handlers such that functions that start with `log_formatted` have the format string coerced to `"%s"` and also have an alias without the `_formatted` part.
2025-09-20 16:14:07 +01:00
github-actions[bot]
6b3a7e2440
Bump version
2025-09-20 00:21:36 +00:00
KrystalDelusion
230855b3f9
Merge pull request #5364 from YosysHQ/krys/gcc-14
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Bump newest supported GCC
2025-09-20 08:37:06 +12:00
Emil J. Tywoniak
0d8c21129f
rtlil: remove textual RTLIL reference tests for ease of maintenance
2025-09-19 16:23:26 +02:00
Robert O'Callahan
4fe21dd652
Reduce hashops verbiage in OptMergePass
2025-09-19 03:31:46 +00:00
Krystine Sherwin
19667dd6f1
CI: Don't use self-hosted runner on forks
2025-09-19 11:43:22 +12:00
Krystine Sherwin
042aff7c77
Bump test-compile to gcc-14 as newest
2025-09-19 11:39:24 +12:00
KrystalDelusion
259bd6fb33
Merge pull request #5358 from georgerennie/george/help_leak
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help: fix memory leak for -dump-cells-json
2025-09-19 10:15:57 +12:00
Emil J. Tywoniak
96f87aa2d4
simplemap: fix src attribute transfer
2025-09-18 12:59:12 +02:00
github-actions[bot]
a686c5a73c
Bump version
2025-09-18 00:22:24 +00:00
George Rennie
5b099abda4
help: fix memory leak for -dump-cells-json
2025-09-17 16:08:36 +01:00
Jannis Harder
d5053033e4
Merge pull request #5353 from jix/new_bufnorm
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Extended buffer normalization
2025-09-17 16:46:35 +02:00
Jannis Harder
79e05a195d
verilog: Bufnorm cell backend and frontend support
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This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
Jannis Harder
4f239b536b
abc_new: Hide buffered 'z drivers from read/write_xaiger2
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With the updated bufnorm code, buffered 'z drivers are used as anchor
points for undirected connections. These are currently not supported by
read/write_xaiger2, so we temporarily replace those by roughly
equivalent $tribuf cells which will be handled as blackboxes that
properly roundtrip through the xaiger2 front and backend.
2025-09-17 13:56:46 +02:00
Jannis Harder
47b3ee8c8b
write_aiger2: Ignore the $input_port cell during indexing.
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The $input_port cell is added by the bufnorm code to simplify handling
of input ports for new code that uses bufnorm, but the aiger2 backend
does already handle input ports separately, so we just ignore those.
2025-09-17 13:56:46 +02:00
Jannis Harder
4918f37be3
write_aiger2: Treat inout ports as output ports
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With the previous bufnorm implementation inout ports were not supported
at all, so this didn't matter, but with the new bufnorm implementation
they need to be treated as output ports.
2025-09-17 13:56:46 +02:00
Jannis Harder
5f79a6e868
Clean up $buf with 'z inputs, $input_port and $connect cells
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This ensures that entering and leaving bufnorm followed by `opt_clean`
is equivalent to just running `opt_clean`.
Also make sure that 'z-$buf cells get techmapped in a compatible way.
2025-09-17 13:56:46 +02:00
Jannis Harder
d88d6fce87
kernel: Rewrite bufNormalize
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This is a complete rewrite of the RTLIL-kernel-side bufnorm code. This
is done to support inout ports and undirected connections as well as to
allow removal of cells while in bufnorm mode.
This doesn't yet update the (experimental) `bufnorm` pass, so to
manually test the new kernel functionality, it is important to only use
`bufnorm -update` and `bufnorm -reset` which rely entirely on the kernel
functionality. Other modes of the `bufnorm` pass may still fail in the
presence of inout ports or undirected connections.
2025-09-17 13:56:46 +02:00
Jannis Harder
1251e92e3a
Add $input_port and $connect cell types
2025-09-17 13:56:46 +02:00
Jannis Harder
c4f435569f
kernel: Add known_driver method to Wire/SigSpec
2025-09-17 13:56:46 +02:00
Jannis Harder
22423b97c1
kernel: Add RTLIL::PortDir for a combined input and output flag
2025-09-17 13:56:46 +02:00
Jannis Harder
6466b15367
Merge pull request #5351 from jix/xaiger_ponum_fix
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write_xaiger2: Fix output port mapping when opaque boxes are present
2025-09-17 13:56:21 +02:00
Jannis Harder
2d81726459
write_xaiger2: Fix output port mapping when opaque boxes are present
2025-09-17 13:10:04 +02:00
Emil J
73e47ac3fe
Merge pull request #5357 from rocallahan/builtin-ff
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Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
2025-09-17 11:37:16 +02:00
Emil J
0e4e2de8f1
Merge pull request #5354 from rocallahan/more-remove-cstr
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Remove more `.c_str()` calls
2025-09-17 11:17:01 +02:00
Robert O'Callahan
d24488d3a5
Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff()
2025-09-17 03:24:19 +00:00
github-actions[bot]
5e550ddc30
Bump version
2025-09-17 00:22:59 +00:00
Robert O'Callahan
64ffcbc394
Deprecate logv_file_error()
2025-09-16 23:26:38 +00:00
Robert O'Callahan
f80be49fa1
Remove unnecessary .c_str() in EDIF_ macros
2025-09-16 23:14:11 +00:00
Robert O'Callahan
a1141f1a4c
Remove some unnecessary .c_str() calls to the result of unescape_id()
2025-09-16 23:12:14 +00:00
Robert O'Callahan
d276529d46
Remove .c_str() calls from parameters to log_file_info()
2025-09-16 23:06:28 +00:00
Robert O'Callahan
548deba259
Remove .c_str() calls from parameters to log_file_warning()
2025-09-16 23:03:45 +00:00
Robert O'Callahan
a7c46f7b4a
Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()
2025-09-16 23:02:16 +00:00
Robert O'Callahan
d1fd6de6da
Remove .c_str() calls from parameters to log_header()
2025-09-16 23:00:42 +00:00
Robert O'Callahan
5ac6858f26
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
Jannis Harder
b95549b469
Merge pull request #5348 from rocallahan/remove-string_buf
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Remove `string_buf` by making `log_signal()` and `log_const()` return `std::string`
2025-09-16 20:20:56 +02:00
Emil J
7bbd0595bb
Merge pull request #5347 from rocallahan/fix-subcircuit
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Fix `subcircuit` building without `#define _YOSYS_`
2025-09-16 17:01:45 +02:00
Emil J
d52d2772d0
Merge pull request #5328 from rhanqtl/issue-5234
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fix(parse): #5234 adjust width of rhs according to lhs
2025-09-16 17:00:46 +02:00
Emil J. Tywoniak
85bcdee232
rtlil: fix roundtrip test on macOS due to sed non-POSIX non-sense
2025-09-16 15:47:38 +02:00
Emil J. Tywoniak
7e6126f753
rtlil: fix roundtrip test by eliminating absolute paths from src attributes with -relativeshare
2025-09-16 15:47:38 +02:00
Emil J. Tywoniak
73747f6928
read_verilog: add -relativeshare for synthesis reproducibility testing
2025-09-16 15:47:35 +02:00
Emil J. Tywoniak
175e024033
functional: in test, rely less on wreduce doing a perfect job
2025-09-16 15:47:16 +02:00
Emil J. Tywoniak
70e681ba7d
rtlil: move test temporary files to temp directory
2025-09-16 15:47:16 +02:00
Emil J. Tywoniak
fdbdd193c1
rtlil: add roundtrip test for design -stash and design -save, fix #5321
2025-09-16 15:47:16 +02:00
Emil J. Tywoniak
4215f3c134
rtlil: add textual roundtrip test
2025-09-16 15:47:16 +02:00
Emil J. Tywoniak
bcc69d5f6e
write_rtlil: add -sort to match old behavior
2025-09-16 15:47:16 +02:00
Emil J. Tywoniak
118c1890b1
raise_error: don't rely on module ordering in test
2025-09-16 15:47:16 +02:00
Emil J. Tywoniak
1328a33e82
write_rtlil: dump in insertion order
2025-09-16 15:47:14 +02:00
Emil J. Tywoniak
68ad52c6ae
bugpoint: don't sort
2025-09-16 15:39:13 +02:00
Emil J. Tywoniak
e11ea42af0
raise_error: whitespace
2025-09-16 15:39:13 +02:00
