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Code Activity
16783 commits 119 branches 65 tags 54 MiB
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Author SHA1 Message Date
Lofty
da83c93673 analogdevices: fix SHIFTX name 2026-03-05 05:37:13 +00:00
Lofty
f3efa51b3e analogdevices: fix SHREG name 2026-03-05 05:37:13 +00:00
Lofty
e2e8245be9 analogdevices: fix MUXF78 name 2026-03-05 05:37:13 +00:00
Lofty
c747466a7a analogdevices: update missed T40LP timings 2026-03-05 05:37:13 +00:00
Lofty
91740645a9 analogdevices: update T40LP timings 2026-03-05 05:37:13 +00:00
Lofty
709746b184 analogdevices: update T16FFC timings 2026-03-05 05:37:13 +00:00
Lofty
cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Lofty
241db706e1 analogdevices: double LUT RAM cost 2026-03-05 05:37:13 +00:00
Lofty
3592d42d3b analogdevices: ignore $assert cells 2026-03-05 05:37:13 +00:00
Krystine Sherwin
5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Krystine Sherwin
f06018306d analogdevices: Fixing up bram 
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
 2026-03-05 05:37:13 +00:00
Krystine Sherwin
95ef0cd788 analogdevices: Add BRAM options 
Enable `-force-params`, and tidy up lutram mapping too.
 2026-03-05 05:37:13 +00:00
Lofty
8a09cc5463 analogdevices: LUT RAM only on positive edge 2026-03-05 05:37:13 +00:00
Lofty
dea8c275ff analogdevices: DSP tweaks 2026-03-05 05:37:12 +00:00
Lofty
39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Lofty
891b89f60d analogdevices: remove cells_xtra 2026-03-05 05:37:12 +00:00
Lofty
4954fc980f analogdevices: timings for t40lp 2026-03-05 05:37:12 +00:00
Lofty
2c3876671b analogdevices: use single tech param 2026-03-05 05:37:12 +00:00
Lofty
0a2b6a4f21 analogdevices: expreso does not care about clock buffers 2026-03-05 05:37:12 +00:00
Lofty
6ee0bfa913 analogdevices: prepare for t40lp timings 2026-03-05 05:37:12 +00:00
Krystine Sherwin
9dcffc3dbf analogdevices: Adding RBRAM2 and -tech 2026-03-05 05:37:12 +00:00
Krystine Sherwin
99e26d80b0 analogdevices: (some) Native BRAM 
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
 2026-03-05 05:37:12 +00:00
Krystine Sherwin
9be3cfb3f9 analogdevices: Update lutram.ys test 2026-03-05 05:37:12 +00:00
Krystine Sherwin
376f746bc9 analogdevices: Native LUTRAM primitives 2026-03-05 05:37:12 +00:00
Lofty
30a03886a5 analogdevices: LUTRAM config 2026-03-05 05:37:12 +00:00
Lofty
ae5325fe53 analogdevices: update timing model 2026-03-05 05:37:12 +00:00
Lofty
c4bec4e8b8 I thought I removed this... 2026-03-05 05:37:12 +00:00
Lofty
85eb07d14d analogdevices: user retargeting 2026-03-05 05:37:12 +00:00
Lofty
c9f6d7b2d4 analogdevices: more housekeeping 2026-03-05 05:37:12 +00:00
Lofty
f659cbd159 analogdevices: remove some extra cells! 2026-03-05 05:37:12 +00:00
Lofty
6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Lofty
4f2f064262 synth_analogdevices: remove scopeinfo cells 2026-03-05 05:37:12 +00:00
Lofty
d5ea7f7016 Create synth_analogdevices 2026-03-05 05:37:12 +00:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
Emil J. Tywoniak
6485a13809 newcelltypes: mark header unstable 2026-03-04 15:17:26 +01:00
Miodrag Milanović
3bc26ff4d0
Merge pull request #5723 from YosysHQ/micko/merge_queue 
CI: add support for merge queue
 2026-03-04 13:18:09 +01:00
nella
16b1a914f1 Aiger use defines for known ops. 2026-03-04 12:39:45 +01:00
nella
04822c6660 Readd builtin_ff_cell_types for plugin parity. 2026-03-04 12:39:45 +01:00
nella
b8ee0803ab Remove todo. 2026-03-04 12:39:45 +01:00
nella
66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
nella
cae54a4c7b Aiger use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
6d4736269b newcelltypes: extend testing 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
0284595e9c celltypes: fix absurd eval declarations 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
793a3513c6 newcelltypes: use unordered_map 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ae10e9e955 pyosys: disable test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
661fcb24cb newcelltypes: fix MSVC build 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
f594014bef newcelltypes: proper bounds for unit test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
12412d1fa5 register: use newcelltypes 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
5216d32d1b yosys: use newcelltypes for yosys_celltypes 2026-03-04 12:22:47 +01:00