mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-11 11:43:38 +00:00
Code Activity
4064 commits 98 branches 53 tags 64 MiB
Commit graph

1 commit

Author SHA1 Message Date
Ruben Undheim d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00